Lines Matching refs:r1
61 ldr r1, __cache_params
71 stmia r1, {r2, r3}
159 ldr r1, __cache_params
160 ldmia r1, {r1, r3}
161 1: orr ip, r1, r3
165 subs r1, r1, #(1 << 5) @ next set
186 sub r3, r1, r0 @ calculate total size
196 cmp r0, r1
232 cmp r0, r1
249 add r1, r0, r1
252 cmp r0, r1
262 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
266 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
291 tst r1, #CACHE_DLINESIZE - 1
292 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
295 cmp r0, r1
305 tst r1, #CACHE_DLINESIZE - 1
306 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
307 cmp r1, r0
308 subne r1, r1, #1 @ top address is inclusive
312 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
331 cmp r0, r1
339 cmp r1, r0
340 subne r1, r1, #1 @ top address is inclusive
344 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
362 cmp r0, r1
370 cmp r1, r0
371 subne r1, r1, #1 @ top address is inclusive
375 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
387 add r1, r1, r0
401 add r1, r1, r0
450 mov r3, r1
454 subs r1, r1, #CACHE_DLINESIZE
537 mcr p15, 0, r1, c2, c0, 0 @ TTB address