Lines Matching refs:r0
60 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
63 tst r0, #(1 << 16) @ get way
64 mov r0, r0, lsr #18 @ get cache size order
66 and r0, r0, #0xf
68 mov r2, r2, lsl r0 @ actual cache size
80 mov r0, #0
81 mcr p15, 1, r0, c15, c9, 0 @ clean L2
82 mcr p15, 0, r0, c7, c10, 4 @ drain WB
85 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
86 bic r0, r0, #0x1000 @ ...i............
87 bic r0, r0, #0x000e @ ............wca.
88 mcr p15, 0, r0, c1, c0, 0 @ disable caches
113 ret r0
124 mov r0, #0
125 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
126 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
135 mov r0, #0
136 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
186 sub r3, r1, r0 @ calculate total size
190 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
191 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
192 add r0, r0, #CACHE_DLINESIZE
193 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
194 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
195 add r0, r0, #CACHE_DLINESIZE
196 cmp r0, r1
228 bic r0, r0, #CACHE_DLINESIZE - 1
229 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
231 add r0, r0, #CACHE_DLINESIZE
232 cmp r0, r1
234 mcr p15, 0, r0, c7, c10, 4 @ drain WB
235 mov r0, #0
249 add r1, r0, r1
250 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
251 add r0, r0, #CACHE_DLINESIZE
252 cmp r0, r1
254 mov r0, #0
255 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
256 mcr p15, 0, r0, c7, c10, 4 @ drain WB
262 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
265 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
268 mov r0, #0
269 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
270 mcr p15, 0, r0, c7, c10, 4 @ drain WB
288 tst r0, #CACHE_DLINESIZE - 1
289 bic r0, r0, #CACHE_DLINESIZE - 1
290 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
293 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
294 add r0, r0, #CACHE_DLINESIZE
295 cmp r0, r1
297 mcr p15, 0, r0, c7, c10, 4 @ drain WB
303 tst r0, #CACHE_DLINESIZE - 1
304 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
307 cmp r1, r0
311 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
328 bic r0, r0, #CACHE_DLINESIZE - 1
329 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
330 add r0, r0, #CACHE_DLINESIZE
331 cmp r0, r1
333 mcr p15, 0, r0, c7, c10, 4 @ drain WB
339 cmp r1, r0
343 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
346 mcr p15, 0, r0, c7, c10, 4 @ drain WB
359 bic r0, r0, #CACHE_DLINESIZE - 1
360 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
361 add r0, r0, #CACHE_DLINESIZE
362 cmp r0, r1
364 mcr p15, 0, r0, c7, c10, 4 @ drain WB
370 cmp r1, r0
374 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
377 mcr p15, 0, r0, c7, c10, 4 @ drain WB
387 add r1, r1, r0
401 add r1, r1, r0
449 mov r2, r0
452 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
453 add r0, r0, #CACHE_DLINESIZE
463 mcr p15, 0, r0, c7, c10, 4 @ drain WB
491 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
507 mov r0, r0
508 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
511 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
513 mcr p15, 0, r0, c7, c10, 4 @ drain WB
526 stmia r0, {r4 - r6}
534 ldmia r0, {r4 - r6}
538 mov r0, r6 @ control register
545 mov r0, #0
546 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
547 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
549 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
554 mrc p15, 0, r0, c1, c0 @ get control register v4
555 bic r0, r0, r5
556 orr r0, r0, r6