Lines Matching refs:invalidate
104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
136 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
162 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
170 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
190 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
191 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
193 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
194 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
250 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
255 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
269 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
293 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
360 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
488 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
492 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
532 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
533 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
546 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
549 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4