Lines Matching refs:c0
47 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
50 mcr p15, 0, r0, c1, c0, 0 @ disable caches
64 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
343 mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
356 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
357 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
363 mcr p15, 0, r0, c3, c0, 0
376 mcr p15, 0, r0, c5, c0, 2 @ set data access permission
377 mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
379 mrc p15, 0, r0, c1, c0 @ get control register