Lines Matching refs:r0
40 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
41 bic r0, r0, #0x00001000 @ i-cache
42 bic r0, r0, #0x00000004 @ d-cache
43 mcr p15, 0, r0, c1, c0, 0 @ disable caches
61 ret r0
70 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
79 mov r0, #0
80 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
163 mov r0, #0
171 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
172 mcr p15, 0, r0, c7, c10, 4 @ drain WB
253 add r1, r1, r0
278 mov r0, #0
279 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
280 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
281 mcr p15, 0, r0, c7, c10, 4 @ drain WB
283 mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
284 mcr p15, 0, r0, c6, c4, 0
285 mcr p15, 0, r0, c6, c5, 0
286 mcr p15, 0, r0, c6, c6, 0
287 mcr p15, 0, r0, c6, c7, 0
289 mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
290 mcr p15, 0, r0, c6, c4, 1
291 mcr p15, 0, r0, c6, c5, 1
292 mcr p15, 0, r0, c6, c6, 1
293 mcr p15, 0, r0, c6, c7, 1
295 mov r0, #0x0000003F @ base = 0, size = 4GB
296 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
297 mcr p15, 0, r0, c6, c0, 1
299 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
301 pr_val r3, r0, r7, #1
305 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
307 pr_val r3, r0, r6, #1
311 mov r0, #0x06
312 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
313 mcr p15, 0, r0, c2, c0, 1
315 mov r0, #0x00 @ disable whole write buffer
317 mov r0, #0x02 @ Region 1 write bufferred
319 mcr p15, 0, r0, c3, c0, 0
321 mov r0, #0x10000
322 sub r0, r0, #1 @ r0 = 0xffff
323 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
324 mcr p15, 0, r0, c5, c0, 1
326 mrc p15, 0, r0, c1, c0 @ get control register
327 orr r0, r0, #0x00001000 @ I-cache
328 orr r0, r0, #0x00000005 @ MPU/D-cache