Lines Matching refs:r0
72 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
73 bic r0, r0, #0x1000 @ ...i............
74 bic r0, r0, #0x000e @ ............wca.
75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
100 ret r0
109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
121 mov r0, #0
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
168 sub r3, r1, r0 @ calculate total size
172 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
175 add r0, r0, #CACHE_DLINESIZE
176 cmp r0, r1
206 bic r0, r0, #CACHE_DLINESIZE - 1
207 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
208 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
209 add r0, r0, #CACHE_DLINESIZE
210 cmp r0, r1
212 mcr p15, 0, r0, c7, c10, 4 @ drain WB
213 mov r0, #0
226 add r1, r0, r1
227 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
228 add r0, r0, #CACHE_DLINESIZE
229 cmp r0, r1
231 mov r0, #0
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
233 mcr p15, 0, r0, c7, c10, 4 @ drain WB
250 tst r0, #CACHE_DLINESIZE - 1
251 bic r0, r0, #CACHE_DLINESIZE - 1
252 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
255 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
256 add r0, r0, #CACHE_DLINESIZE
257 cmp r0, r1
259 mcr p15, 0, r0, c7, c10, 4 @ drain WB
273 bic r0, r0, #CACHE_DLINESIZE - 1
274 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
275 add r0, r0, #CACHE_DLINESIZE
276 cmp r0, r1
278 mcr p15, 0, r0, c7, c10, 4 @ drain WB
290 bic r0, r0, #CACHE_DLINESIZE - 1
291 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
292 add r0, r0, #CACHE_DLINESIZE
293 cmp r0, r1
295 mcr p15, 0, r0, c7, c10, 4 @ drain WB
305 add r1, r1, r0
331 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
332 add r0, r0, #CACHE_DLINESIZE
367 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
381 mov r0, r0
382 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
383 mcr p15, 0, r0, c7, c10, 4 @ drain WB
396 stmia r0, {r4 - r6}
404 ldmia r0, {r4 - r6}
408 mov r0, r6 @ control register
415 mov r0, #0
416 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
417 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
419 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
423 mrc p15, 0, r0, c1, c0 @ get control register v4
424 bic r0, r0, r5
425 orr r0, r0, r6