Lines Matching refs:r0
71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
72 bic r0, r0, #0x1000 @ ...i............
73 bic r0, r0, #0x000e @ ............wca.
74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
99 ret r0
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mov r0, #0
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
173 sub r3, r1, r0 @ calculate total size
178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
179 add r0, r0, #CACHE_DLINESIZE
180 cmp r0, r1
215 bic r0, r0, #CACHE_DLINESIZE - 1
218 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
223 add r0, r0, #CACHE_DLINESIZE
224 cmp r0, r1
227 mov r0, #0
242 add r1, r0, r1
243 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
244 add r0, r0, #CACHE_DLINESIZE
245 cmp r0, r1
267 tst r0, #CACHE_DLINESIZE - 1
268 bic r0, r0, #CACHE_DLINESIZE - 1
269 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
272 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
273 add r0, r0, #CACHE_DLINESIZE
274 cmp r0, r1
293 bic r0, r0, #CACHE_DLINESIZE - 1
294 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
295 add r0, r0, #CACHE_DLINESIZE
296 cmp r0, r1
313 bic r0, r0, #CACHE_DLINESIZE - 1
314 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
315 add r0, r0, #CACHE_DLINESIZE
316 cmp r0, r1
329 add r1, r1, r0
356 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
357 add r0, r0, #CACHE_DLINESIZE
389 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
403 mov r0, r0
405 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
412 mov r0, #0
413 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
414 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
416 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
420 mrc p15, 0, r0, c1, c0 @ get control register v4
421 bic r0, r0, r5
422 orr r0, r0, r6
424 orr r0, r0, #0x4000 @ .R..............