Lines Matching refs:r1
39 movw r1, #0x7fff
40 and r2, r1, r0, lsr #13
42 movw r1, #0x3ff
44 and r3, r1, r0, lsr #3 @ NumWays - 1
50 clz r1, r3 @ WayShift
55 mov r5, r3, lsl r1
100 movw r1, #:lower16:(0x410fc090 >> 4) @ ID of ARM Cortex A9 r0p?
101 movt r1, #:upper16:(0x410fc090 >> 4)
102 teq r1, r2, lsr #4 @ test for errata affected core and if so...
128 mov r1, r0, lsr r2 @ extract cache type bits from clidr
129 and r1, r1, #7 @ mask of the bits for current cache only
130 cmp r1, #2 @ see what cache we have at this level
137 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
141 and r2, r1, #7 @ extract the length of the cache lines
144 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
147 ands r7, r7, r1, lsr #13 @ extract max number of the index size
283 cmp r12, r1
292 cmp r12, r1
326 add r1, r0, r1
336 cmp r0, r1
363 tst r1, r3
364 bic r1, r1, r3
365 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
369 cmp r0, r1
391 cmp r0, r1
413 cmp r0, r1
426 add r1, r1, r0
439 add r1, r1, r0