Lines Matching refs:r6

62 	and	r6, r8, r7
64 	add	r6, r6, r9, lsr #1
66 	add	r6, r6, r9, lsr #2
68 	add	r6, r6, r9, lsr #3
69 	add	r6, r6, r6, lsr #8
70 	add	r6, r6, r6, lsr #4
71 	and	r6, r6, #15			@ r6 = no. of registers to transfer.
75 	subne	r7, r7, r6, lsl #2		@ Undo increment
76 	addeq	r7, r7, r6, lsl #2		@ Undo decrement
86 	andne	r6, r8, #0xf00			@ { immediate high nibble
87 	orrne	r6, r9, r6, lsr #4		@   combine nibbles } else
88 	ldreq	r6, [r2, r9, lsl #2]		@ { load Rm value }
93 	subne	r7, r7, r6			@ Undo incrmenet
94 	addeq	r7, r7, r6			@ Undo decrement
102 	movs	r6, r8, lsl #20			@ Get offset
107 	subne	r7, r7, r6, lsr #20		@ Undo increment
108 	addeq	r7, r7, r6, lsr #20		@ Undo decrement
117 	ldr	r6, [r2, r7, lsl #2]		@ Get register 'Rm'
125 	mov	r6, r6, lsl r9			@ 0: LSL #!0
133 	mov	r6, r6, lsr r9			@ 4: LSR #!0
135 	mov	r6, r6, lsr #32			@ 5: LSR #32
141 	mov	r6, r6, asr r9			@ 8: ASR #!0
143 	mov	r6, r6, asr #32			@ 9: ASR #32
149 	mov	r6, r6, ror r9			@ C: ROR #!0
151 	mov	r6, r6, rrx			@ D: RRX
193 	and	r6, r8, #0x55			@ hweight8(r8) + R bit
195 	add	r6, r6, r9, lsr #1
196 	and	r9, r6, #0xcc
197 	and	r6, r6, #0x33
198 	add	r6, r6, r9, lsr #2
200 	adc	r6, r6, r6, lsr #4		@ high + low nibble + R bit
201 	and	r6, r6, #15			@ number of regs to transfer
204 	addeq	r7, r7, r6, lsl #2		@ increment SP if PUSH
205 	subne	r7, r7, r6, lsl #2		@ decrement SP if POP
210 	and	r6, r8, #0x55			@ hweight8(r8)
212 	add	r6, r6, r9, lsr #1
213 	and	r9, r6, #0xcc
214 	and	r6, r6, #0x33
215 	add	r6, r6, r9, lsr #2
216 	add	r6, r6, r6, lsr #4
219 	and	r6, r6, #15			@ number of regs to transfer
220 	sub	r7, r7, r6, lsl #2		@ always decrement