Lines Matching refs:instruction

4 # which CPUs we support in the kernel image, and the compiler instruction
103 	  instruction and data caches. It is used in Altera's
122 	  different instruction and data caches. It is used in TI's OMAP
140 	  instruction sequences for cache and TLB operations.  Curiously,
176 	  instruction and 4KB data cases, each with a 4-word line
194 	  The TCM and ARMv5TE 32-bit instruction set is supported.
418 # This defines the compiler instruction set which depends on the machine type.
550 	  instruction cache entry.
561 	  and invalidate instruction cache entry. Branch target buffer is
661 	  The Thumb instruction set is a compressed form of the standard ARM
662 	  instruction set resulting in smaller binaries at the expense of
695 	  these instructions, triggering an undefined instruction exception
752 	  Say Y here to disable the processor instruction cache. Unless