Lines Matching refs:word
538 .word TEGRA_EMC_BASE + EMC_CFG @0x0
539 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
540 .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
541 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
542 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
543 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
544 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
545 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
549 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
550 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
551 .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8
552 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc
553 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
554 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
555 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
556 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
557 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
558 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
559 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
560 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
561 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
565 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
566 .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
567 .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
568 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
569 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
570 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
571 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
572 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
576 .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
579 .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address