Lines Matching refs:r1
187 str r12, [r1]
195 ldr r3, [r1] @ read CSR
196 str r3, [r1] @ clear CSR
265 mov32 r1, tegra30_iram_start
266 sub r0, r0, r1
267 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
268 add r0, r0, r1
329 mov r1, #(1 << 28)
330 str r1, [r0, #CLK_RESET_SCLK_BURST]
331 str r1, [r0, #CLK_RESET_CCLK_BURST]
332 mov r1, #0
333 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
334 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
340 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
341 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
342 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
345 ldr r1, [r7]
346 add r1, r1, #2
347 wait_until r1, r7, r3
351 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
352 orr r1, r1, #(1 << 12)
353 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
355 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
356 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
357 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
364 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
365 orr r1, r1, #(1 << 12)
366 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
368 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
369 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
370 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
373 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
374 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
376 pll_locked r1, r0, CLK_RESET_PLLM_BASE
377 pll_locked r1, r0, CLK_RESET_PLLP_BASE
378 pll_locked r1, r0, CLK_RESET_PLLA_BASE
379 pll_locked r1, r0, CLK_RESET_PLLC_BASE
380 pll_locked r1, r0, CLK_RESET_PLLX_BASE
383 ldr r1, [r7]
384 add r1, r1, #LOCK_DELAY
385 wait_until r1, r7, r3
403 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
404 mvn r1, r1
405 bic r1, r1, #(1 << 31)
406 orr r1, r1, #(1 << 30)
407 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
420 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
421 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
422 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
423 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
424 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
425 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
428 ldr r1, [r0, #EMC_CFG_DIG_DLL]
429 orr r1, r1, #(1 << 30) @ set DLL_RESET
430 str r1, [r0, #EMC_CFG_DIG_DLL]
432 emc_timing_update r1, r0
435 movweq r1, #:lower16:TEGRA_EMC1_BASE
436 movteq r1, #:upper16:TEGRA_EMC1_BASE
437 cmpeq r0, r1
439 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
440 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
441 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
442 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
445 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
446 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
449 ldr r1, [r0, #EMC_CFG]
450 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
451 str r1, [r0, #EMC_CFG]
453 mov r1, #0
454 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
455 mov r1, #1
457 streq r1, [r0, #EMC_NOP]
458 streq r1, [r0, #EMC_NOP]
459 streq r1, [r0, #EMC_REFRESH]
461 emc_device_mask r1, r0
465 ands r2, r2, r1
468 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
484 tst r1, #2
503 tst r1, #2
514 mov r1, #0 @ unstall all transactions
515 str r1, [r0, #EMC_REQ_CTRL]
516 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
517 str r1, [r0, #EMC_ZCAL_INTERVAL]
518 ldr r1, [r5, #0x0] @ restore EMC_CFG
519 str r1, [r0, #EMC_CFG]
524 mov32 r1, TEGRA_EMC1_BASE
525 cmp r0, r1
526 movne r0, r1
617 ldr r1, [r7]
618 add r1, r1, #2
619 wait_until r1, r7, r9
631 ldr r1, [r7]
632 add r1, r1, #2
633 wait_until r1, r7, r9
656 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
674 cpu_id r1
676 cpu_to_csr_reg r2, r1
688 cpu_to_halt_reg r2, r1
731 ldr r1, [r0]
732 str r1, [r8, r9] @ save the content of the addr
750 mov r1, #0
751 str r1, [r0, #EMC_ZCAL_INTERVAL]
752 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
753 ldr r1, [r0, #EMC_CFG]
754 bic r1, r1, #(1 << 28)
755 bicne r1, r1, #(1 << 29)
756 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
758 emc_timing_update r1, r0
760 ldr r1, [r7]
761 add r1, r1, #5
762 wait_until r1, r7, r2
765 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
766 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
769 mov r1, #3
770 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
773 ldr r1, [r0, #EMC_EMC_STATUS]
774 tst r1, #4
777 mov r1, #1
778 str r1, [r0, #EMC_SELF_REF]
780 emc_device_mask r1, r0
784 and r2, r2, r1
785 cmp r2, r1
789 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
791 and r1, r1, r2
792 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
793 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
795 orreq r1, r1, #7 @ set E_NO_VTTGEN
796 orrne r1, r1, #0x3f
797 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
799 emc_timing_update r1, r0
804 mov32 r1, TEGRA_EMC1_BASE
805 cmp r0, r1
806 movne r0, r1
810 ldr r1, [r4, #PMC_CTRL]
811 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
817 mov32 r1, 0x8EC00000
818 str r1, [r4, #PMC_IO_DPD_REQ]