Lines Matching refs:r0
144 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
198 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
214 ldr r0, [r2]
262 add r3, r3, r0
264 mov32 r0, tegra30_tear_down_core
266 sub r0, r0, r1
268 add r0, r0, r1
282 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
286 mov r0, #0 @ power mode flags (!hotplug)
288 mov r0, #1 @ never return here
327 mov32 r0, TEGRA_CLK_RESET_BASE
330 str r1, [r0, #CLK_RESET_SCLK_BURST]
331 str r1, [r0, #CLK_RESET_CCLK_BURST]
333 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
334 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
340 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
341 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
342 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
355 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
356 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
357 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
368 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
369 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
370 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
373 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
374 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
376 pll_locked r1, r0, CLK_RESET_PLLM_BASE
377 pll_locked r1, r0, CLK_RESET_PLLP_BASE
378 pll_locked r1, r0, CLK_RESET_PLLA_BASE
379 pll_locked r1, r0, CLK_RESET_PLLC_BASE
380 pll_locked r1, r0, CLK_RESET_PLLX_BASE
390 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
393 str r4, [r0, #CLK_RESET_SCLK_BURST]
400 str r4, [r0, #CLK_RESET_CCLK_BURST]
410 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
411 movteq r0, #:upper16:TEGRA_EMC_BASE
413 movweq r0, #:lower16:TEGRA_EMC0_BASE
414 movteq r0, #:upper16:TEGRA_EMC0_BASE
416 movweq r0, #:lower16:TEGRA124_EMC_BASE
417 movteq r0, #:upper16:TEGRA124_EMC_BASE
421 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
423 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
425 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
428 ldr r1, [r0, #EMC_CFG_DIG_DLL]
430 str r1, [r0, #EMC_CFG_DIG_DLL]
432 emc_timing_update r1, r0
437 cmpeq r0, r1
439 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
442 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
445 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
449 ldr r1, [r0, #EMC_CFG]
451 str r1, [r0, #EMC_CFG]
454 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
457 streq r1, [r0, #EMC_NOP]
458 streq r1, [r0, #EMC_NOP]
459 streq r1, [r0, #EMC_REFRESH]
461 emc_device_mask r1, r0
464 ldr r2, [r0, #EMC_EMC_STATUS]
471 ldr r2, [r0, #EMC_FBIO_CFG5]
479 str r2, [r0, #EMC_ZQ_CAL]
489 str r2, [r0, #EMC_ZQ_CAL]
498 str r2, [r0, #EMC_MRW]
508 str r2, [r0, #EMC_MRW]
515 str r1, [r0, #EMC_REQ_CTRL]
517 str r1, [r0, #EMC_ZCAL_INTERVAL]
519 str r1, [r0, #EMC_CFG]
525 cmp r0, r1
526 movne r0, r1
531 mov32 r0, TEGRA_PMC_BASE
532 ldr r0, [r0, #PMC_SCRATCH41]
533 ret r0 @ jump to tegra_resume
614 mov r0, #(1 << 28)
615 str r0, [r5, #CLK_RESET_SCLK_BURST]
620 str r0, [r5, #CLK_RESET_CCLK_BURST]
621 mov r0, #0
622 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
623 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
626 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
627 orr r0, r0, #MSELECT_CLKM
628 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
636 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
637 bic r0, r0, #(1 << 12)
638 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
641 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
642 bic r0, r0, #(1 << 30)
643 str r0, [r5, #CLK_RESET_PLLP_BASE]
644 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
645 bic r0, r0, #(1 << 30)
646 str r0, [r5, #CLK_RESET_PLLA_BASE]
647 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
648 bic r0, r0, #(1 << 30)
649 str r0, [r5, #CLK_RESET_PLLC_BASE]
650 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
651 bic r0, r0, #(1 << 30)
652 str r0, [r5, #CLK_RESET_PLLX_BASE]
660 mov r0, #0 /* brust policy = 32KHz */
661 str r0, [r5, #CLK_RESET_SCLK_BURST]
677 ldr r0, [r6, r2]
678 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
679 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
680 str r0, [r6, r2]
684 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
685 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
686 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
689 str r0, [r6, r2]
691 ldr r0, [r6, r2] /* memory barrier */
729 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
731 ldr r1, [r0]
742 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
744 ldreq r0, =TEGRA_EMC0_BASE
746 ldreq r0, =TEGRA124_EMC_BASE
751 str r1, [r0, #EMC_ZCAL_INTERVAL]
752 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
753 ldr r1, [r0, #EMC_CFG]
756 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
758 emc_timing_update r1, r0
765 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
770 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
773 ldr r1, [r0, #EMC_EMC_STATUS]
778 str r1, [r0, #EMC_SELF_REF]
780 emc_device_mask r1, r0
783 ldr r2, [r0, #EMC_EMC_STATUS]
789 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
792 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
793 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
797 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
799 emc_timing_update r1, r0
805 cmp r0, r1
806 movne r0, r1