Lines Matching refs:r3
106 ldr r3, =TEGRA_FLOW_CTRL_VIRT
108 str r2, [r3, r1] @ put flow controller in wait event mode
109 ldr r2, [r3, r1]
114 ldr r3, =TEGRA_CLK_RESET_VIRT
115 str r1, [r3, #0x340] @ put slave CPU in reset
118 cpu_id r3
119 cmp r3, r0
148 mov32 r3, TEGRA_PMC_VIRT
150 add r1, r3, #PMC_SCRATCH37
152 addeq r2, r3, #PMC_SCRATCH38
153 addeq r3, r3, #PMC_SCRATCH39
154 addne r2, r3, #PMC_SCRATCH39
155 addne r3, r3, #PMC_SCRATCH38
162 ldr r12, [r3]
173 mov32 r3, TEGRA_PMC_VIRT
176 addeq r2, r3, #PMC_SCRATCH38
177 addne r2, r3, #PMC_SCRATCH39
237 mov32 r3, tegra_shut_off_mmu
238 add r3, r3, r0
246 ret r3
265 mov r3, #CPU_RESETTABLE
266 strb r3, [r0, r4]
284 mov r3, #CPU_NOT_RESETTABLE
285 strb r3, [r0, r4]
513 ldr r3, [r1, #EMC_EMC_STATUS]
514 and r3, r3, r2
515 cmp r3, r2
519 adr r3, tegra20_sdram_pad_safe
530 ldr r1, [r3, r5]