Lines Matching refs:r1
100 mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
103 strb r12, [r1, r2]
105 cpu_to_halt_reg r1, r0
108 str r2, [r3, r1] @ put flow controller in wait event mode
109 ldr r2, [r3, r1]
112 movw r1, 0x1011
113 mov r1, r1, lsl r0
115 str r1, [r3, #0x340] @ put slave CPU in reset
150 add r1, r3, #PMC_SCRATCH37
160 str r12, [r1] @ !turn = cpu
164 ldreq r12, [r1]
190 mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
193 strb r12, [r1, r2]
204 mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
207 strb r12, [r1, r2]
218 mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
220 ldrb r12, [r1, r2]
241 mov32 r1, tegra20_iram_start
242 sub r0, r0, r1
243 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
244 add r0, r0, r1
298 mov r1, #0
299 mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs
300 mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
347 mov r1, #(1 << 28)
348 str r1, [r0, #CLK_RESET_SCLK_BURST]
349 str r1, [r0, #CLK_RESET_CCLK_BURST]
350 mov r1, #0
351 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
352 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
354 pll_enable r1, r0, CLK_RESET_PLLM_BASE
355 pll_enable r1, r0, CLK_RESET_PLLP_BASE
356 pll_enable r1, r0, CLK_RESET_PLLC_BASE
366 ldr r1, [r4, r5]
367 str r1, [r7] @ restore the value in pad_save
376 ldr r1, [r7]
377 add r1, r1, #0xff
378 wait_until r1, r7, r9
387 ldr r1, [r0, #EMC_CFG]
388 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP
389 str r1, [r0, #EMC_CFG]
391 mov r1, #0
392 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
393 mov r1, #1
394 str r1, [r0, #EMC_NOP]
395 str r1, [r0, #EMC_NOP]
396 str r1, [r0, #EMC_REFRESH]
398 emc_device_mask r1, r0
402 ands r2, r2, r1
405 mov r1, #0 @ unstall all transactions
406 str r1, [r0, #EMC_REQ_CTRL]
444 ldr r1, [r7]
445 add r1, r1, #2
446 wait_until r1, r7, r9
477 cpu_id r1
478 cpu_to_halt_reg r1, r1
479 str r0, [r6, r1]
481 ldr r0, [r6, r1] /* memory barrier */
497 mov32 r1, TEGRA_EMC_BASE @ r1 reserved for emc base addr
500 str r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests
503 ldr r2, [r1, #EMC_EMC_STATUS]
508 str r2, [r1, #EMC_SELF_REF]
510 emc_device_mask r2, r1
513 ldr r3, [r1, #EMC_EMC_STATUS]
527 ldr r1, [r0]
528 str r1, [r4, r5] @ save the content of the addr
530 ldr r1, [r3, r5]
531 str r1, [r0] @ set the save val to the addr