Lines Matching refs:r0
79 cpu_id r0
98 cmp r0, #0
105 cpu_to_halt_reg r1, r0
113 mov r1, r1, lsl r0
119 cmp r3, r0
149 cpu_id r0
151 cmp r0, #0
165 cmpeq r12, r0 @ !turn == cpu?
174 cpu_id r0
175 cmp r0, #0
222 moveq r0, #1
223 movne r0, #0
238 add r3, r3, r0
240 mov32 r0, tegra20_tear_down_core
242 sub r0, r0, r1
244 add r0, r0, r1
260 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
263 mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT
266 strb r3, [r0, r4]
282 mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT
285 strb r3, [r0, r4]
345 mov32 r0, TEGRA_CLK_RESET_BASE
348 str r1, [r0, #CLK_RESET_SCLK_BURST]
349 str r1, [r0, #CLK_RESET_CCLK_BURST]
351 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
352 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
354 pll_enable r1, r0, CLK_RESET_PLLM_BASE
355 pll_enable r1, r0, CLK_RESET_PLLP_BASE
356 pll_enable r1, r0, CLK_RESET_PLLC_BASE
382 str r4, [r0, #CLK_RESET_SCLK_BURST]
384 str r4, [r0, #CLK_RESET_CCLK_BURST]
386 mov32 r0, TEGRA_EMC_BASE
387 ldr r1, [r0, #EMC_CFG]
389 str r1, [r0, #EMC_CFG]
392 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
394 str r1, [r0, #EMC_NOP]
395 str r1, [r0, #EMC_NOP]
396 str r1, [r0, #EMC_REFRESH]
398 emc_device_mask r1, r0
401 ldr r2, [r0, #EMC_EMC_STATUS]
406 str r1, [r0, #EMC_REQ_CTRL]
408 mov32 r0, TEGRA_PMC_BASE
409 ldr r0, [r0, #PMC_SCRATCH41]
410 ret r0 @ jump to tegra_resume
435 mov r0, #(1 << 28)
436 str r0, [r5, #CLK_RESET_SCLK_BURST]
437 str r0, [r5, #CLK_RESET_CCLK_BURST]
438 mov r0, #0
439 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
440 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
449 ldr r0, [r5, #CLK_RESET_PLLM_BASE]
450 bic r0, r0, #(1 << 30)
451 str r0, [r5, #CLK_RESET_PLLM_BASE]
452 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
453 bic r0, r0, #(1 << 30)
454 str r0, [r5, #CLK_RESET_PLLP_BASE]
455 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
456 bic r0, r0, #(1 << 30)
457 str r0, [r5, #CLK_RESET_PLLC_BASE]
460 mov r0, #0 /* brust policy = 32KHz */
461 str r0, [r5, #CLK_RESET_SCLK_BURST]
475 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
476 orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
479 str r0, [r6, r1]
481 ldr r0, [r6, r1] /* memory barrier */
525 ldr r0, [r2, r5] @ r0 is the addr in the pad_address
527 ldr r1, [r0]
531 str r1, [r0] @ set the save val to the addr
539 ldr r0, [r5, #CLK_RESET_SCLK_BURST]
541 str r0, [r2]