1385 #define MDCNFG_PrChrg(Tcpu)     	/*  Pre-Charge time [2..32 Tcpu]   */ \  argument
1386                 	(((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
1387 #define MDCNFG_CeilPrChrg(Tcpu) 	/*  Ceil. of PrChrg [2..32 Tcpu]   */ \  argument
1388                 	(((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
1390 #define MDCNFG_Ref(Tcpu)        	/*  Refresh time [2..32 Tcpu]      */ \  argument
1391                 	(((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
1392 #define MDCNFG_CeilRef(Tcpu)    	/*  Ceil. of Ref [2..32 Tcpu]      */ \  argument
1393                 	(((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
1395 #define MDCNFG_DataLtch(Tcpu)   	/*  Data Latch delay [0..3 Tcpu]   */ \  argument
1396                 	((Tcpu) << FShft (MDCNFG_TDL))
1399 #define MDCNFG_RefInt(Tcpu)     	/*  min. Refresh Interval          */ \  argument
1401                 	((Tcpu)/8 << FShft (MDCNFG_DRI))
1467 #define MSC_1stRdAcc(Tcpu)      	/*  1st Read Access time (burst    */ \  argument
1469                 	((((Tcpu) - 3)/2) << FShft (MSC_RDF))
1470 #define MSC_Ceil1stRdAcc(Tcpu)  	/*  Ceil. of 1stRdAcc [3..65 Tcpu] */ \  argument
1471                 	((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1472 #define MSC_RdAcc(Tcpu)	        	/*  Read Access time (non-burst    */ \  argument
1474                 	((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1475 #define MSC_CeilRdAcc(Tcpu)     	/*  Ceil. of RdAcc [2..64 Tcpu]    */ \  argument
1476                 	((((Tcpu) - 1)/2) << FShft (MSC_RDF))
1479 #define MSC_NxtRdAcc(Tcpu)      	/*  Next Read Access time (burst   */ \  argument
1481                 	((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1482 #define MSC_CeilNxtRdAcc(Tcpu)  	/*  Ceil. of NxtRdAcc [2..64 Tcpu] */ \  argument
1483                 	((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1484 #define MSC_WrAcc(Tcpu)	        	/*  Write Access time (non-burst   */ \  argument
1486                 	((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1487 #define MSC_CeilWrAcc(Tcpu)     	/*  Ceil. of WrAcc [2..64 Tcpu]    */ \  argument
1488                 	((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1491 #define MSC_Rec(Tcpu)	        	/*  Recovery time [0..28 Tcpu]     */ \  argument
1492                 	(((Tcpu)/4) << FShft (MSC_RRR))
1493 #define MSC_CeilRec(Tcpu)       	/*  Ceil. of Rec [0..28 Tcpu]      */ \  argument
1494                 	((((Tcpu) + 3)/4) << FShft (MSC_RRR))
1520 #define MECR_IOClk(Tcpu)        	/*  I/O Clock [2..64 Tcpu]         */ \  argument
1521                 	((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
1522 #define MECR_CeilIOClk(Tcpu)    	/*  Ceil. of IOClk [2..64 Tcpu]    */ \  argument
1523                 	((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
1526 #define MECR_AttrClk(Tcpu)      	/*  Attribute Clock [2..64 Tcpu]   */ \  argument
1527                 	((((Tcpu) - 2)/2) << FShft (MECR_BSA))
1528 #define MECR_CeilAttrClk(Tcpu)  	/*  Ceil. of AttrClk [2..64 Tcpu]  */ \  argument
1529                 	((((Tcpu) - 1)/2) << FShft (MECR_BSA))
1531 #define MECR_MemClk(Tcpu)       	/*  Memory Clock [2..64 Tcpu]      */ \  argument
1532                 	((((Tcpu) - 2)/2) << FShft (MECR_BSM))
1533 #define MECR_CeilMemClk(Tcpu)   	/*  Ceil. of MemClk [2..64 Tcpu]   */ \  argument
1534                 	((((Tcpu) - 1)/2) << FShft (MECR_BSM))
1686 #define LCCR0_DMADel(Tcpu)      	/*  palette DMA request Delay      */ \  argument
1688                 	((Tcpu)/2 << FShft (LCCR0_PDD))