Lines Matching refs:FShft
142 (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
148 (((Size) - 1) << FShft (UDCIMP_INMAXP))
342 FShft (UTCR1_BRD))
345 FShft (UTCR2_BRD))
350 FShft (UTCR1_BRD))
353 FShft (UTCR2_BRD))
481 FShft (SDCR3_BRD))
484 FShft (SDCR4_BRD))
489 FShft (SDCR3_BRD))
492 FShft (SDCR4_BRD))
642 ((Div)/32 << FShft (MCCR0_ASD))
646 (((Div) + 31)/32 << FShft (MCCR0_ASD))
655 ((Div)/32 << FShft (MCCR0_TSD))
659 (((Div) + 31)/32 << FShft (MCCR0_TSD))
681 (((Div) - 1) << FShft (MCCR0_ECP))
759 (((Size) - 1) << FShft (SSCR0_DSS))
763 (0 << FShft (SSCR0_FRF))
766 (1 << FShft (SSCR0_FRF))
768 (2 << FShft (SSCR0_FRF))
774 (((Div) - 2)/2 << FShft (SSCR0_SCR))
778 (((Div) - 1)/2 << FShft (SSCR0_SCR))
946 (0x00 << FShft (PPCR_CCF))
948 (0x01 << FShft (PPCR_CCF))
950 (0x02 << FShft (PPCR_CCF))
952 (0x03 << FShft (PPCR_CCF))
954 (0x04 << FShft (PPCR_CCF))
956 (0x05 << FShft (PPCR_CCF))
958 (0x06 << FShft (PPCR_CCF))
960 (0x07 << FShft (PPCR_CCF))
962 (0x08 << FShft (PPCR_CCF))
964 (0x09 << FShft (PPCR_CCF))
966 (0x0A << FShft (PPCR_CCF))
968 (0x0B << FShft (PPCR_CCF))
970 (0x0C << FShft (PPCR_CCF))
972 (0x0D << FShft (PPCR_CCF))
974 (0x0E << FShft (PPCR_CCF))
976 (0x0F << FShft (PPCR_CCF))
1060 (0 << FShft (TUCR_TSEL))
1062 (1 << FShft (TUCR_TSEL))
1064 (2 << FShft (TUCR_TSEL))
1066 (3 << FShft (TUCR_TSEL))
1069 (4 << FShft (TUCR_TSEL))
1072 (5 << FShft (TUCR_TSEL))
1074 (6 << FShft (TUCR_TSEL))
1076 (7 << FShft (TUCR_TSEL))
1381 (((Add) - 9) << FShft (MDCNFG_DRAC))
1386 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
1388 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
1391 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
1393 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
1396 ((Tcpu) << FShft (MDCNFG_TDL))
1401 ((Tcpu)/8 << FShft (MDCNFG_DRI))
1455 (0 << FShft (MSC_RT))
1457 (1 << FShft (MSC_RT))
1459 (2 << FShft (MSC_RT))
1461 (3 << FShft (MSC_RT))
1469 ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
1471 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1474 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1476 ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
1481 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1483 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1486 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1488 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1492 (((Tcpu)/4) << FShft (MSC_RRR))
1494 ((((Tcpu) + 3)/4) << FShft (MSC_RRR))
1521 ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
1523 ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
1527 ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
1529 ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
1532 ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
1534 ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
1633 (0 << FShft (LCD_PBS))
1635 (1 << FShft (LCD_PBS))
1637 (2 << FShft (LCD_PBS))
1688 ((Tcpu)/2 << FShft (LCCR0_PDD))
1713 (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
1718 (((Tpix) - 1) << FShft (LCCR1_HSW))
1723 (((Tpix) - 1) << FShft (LCCR1_ELW))
1728 (((Tpix) - 1) << FShft (LCCR1_BLW))
1732 (((Line) - 1) << FShft (LCCR2_LPP))
1737 (((Tln) - 1) << FShft (LCCR2_VSW))
1742 ((Tln) << FShft (LCCR2_EFW))
1747 ((Tln) << FShft (LCCR2_BFW))
1754 (((Div) - 4)/2 << FShft (LCCR3_PCD))
1758 (((Div) - 3)/2 << FShft (LCCR3_PCD))
1764 (((Div) - 2)/2 << FShft (LCCR3_ACB))
1768 (((Div) - 1)/2 << FShft (LCCR3_ACB))
1775 (0 << FShft (LCCR3_API))
1778 ((Trans) << FShft (LCCR3_API))