Lines Matching refs:BIT
74 #define GRF_SIDDQ BIT(13)
126 mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) | in rk3288_slp_mode_set()
127 BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) | in rk3288_slp_mode_set()
128 BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) | in rk3288_slp_mode_set()
129 BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) | in rk3288_slp_mode_set()
130 BIT(PMU_SCU_EN); in rk3288_slp_mode_set()
132 mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP); in rk3288_slp_mode_set()
136 mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) | in rk3288_slp_mode_set()
137 BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) | in rk3288_slp_mode_set()
138 BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN); in rk3288_slp_mode_set()
141 mode_set |= BIT(PMU_OSC_24M_DIS); in rk3288_slp_mode_set()
143 mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) | in rk3288_slp_mode_set()
144 BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA); in rk3288_slp_mode_set()
167 mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN); in rk3288_slp_mode_set()