Lines Matching refs:r1
23 mov r1, #(PSSR_PH | PSSR_STS)
31 str r1, [r0] @ make sure PSSR_PH/STS are clear
51 mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG)
52 add r1, r1, #0x00100000
62 ldr r2, [r1] @ Dummy read PXA3_MDCNFG
69 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
71 str r0, [r1, #PXA3_DDR_HCAL]
72 1: ldr r0, [r1, #PXA3_DDR_HCAL]
76 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
78 str r0, [r1, #PXA3_RCOMP]
81 str r0, [r1, #PXA3_DMCISR]
83 ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
85 str r0, [r1, #PXA3_DMCIER]
87 ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
90 str r0, [r1, #PXA3_DDR_HCAL]
92 1: ldr r0, [r1, #PXA3_DMCISR]
96 ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
98 str r0, [r1, #PXA3_MDCNFG]
99 1: ldr r0, [r1, #PXA3_MDCNFG]
103 ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
105 str r0, [r1, #PXA3_DDR_HCAL]
107 ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
109 str r0, [r1, #PXA3_DMCIER]