Lines Matching refs:r0
63 cmp r0, #0x0
71 ldr r9, [r0, #OMAP_TYPE_OFFSET]
74 mov r0, #SCU_PM_NORMAL
88 mrc p15, 0, r0, c1, c0, 0
89 bic r0, r0, #(1 << 2) @ Disable the C bit
90 mcr p15, 0, r0, c1, c0, 0
109 mov r8, r0
113 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
114 ands r0, r0, #0x0f
115 ldreq r0, [r8, #SCU_OFFSET0]
116 ldrne r0, [r8, #SCU_OFFSET1]
124 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
125 ands r0, r0, #0x0f
131 mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data
132 tst r0, #(1 << 18)
133 mrcne p15, 0, r0, c1, c0, 1
134 bicne r0, r0, #(1 << 6) @ Disable SMP bit
135 mcrne p15, 0, r0, c1, c0, 1
150 mov r8, r0
153 ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
154 ldrne r0, [r8, #L2X0_SAVE_OFFSET1] @ memory.
155 cmp r0, #3
158 mov r0, #0x03
163 mov r2, r0
164 ldr r0, =0xffff
165 str r0, [r2, #L2X0_CLEAN_INV_WAY]
167 ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
169 ands r0, r0, r1
172 mov r0, #0x00
178 mov r2, r0
179 mov r0, #0x0
180 str r0, [r2, #L2X0_CACHE_SYNC]
182 ldr r0, [r2, #L2X0_CACHE_SYNC]
183 ands r0, r0, #0x1
194 mrc p15, 0, r0, c1, c0, 0
195 tst r0, #(1 << 2) @ Check C bit enabled?
196 orreq r0, r0, #(1 << 2) @ Enable the C bit
197 mcreq p15, 0, r0, c1, c0, 0
206 mrc p15, 0, r0, c1, c0, 1
207 tst r0, #(1 << 6) @ Check SMP bit enabled?
208 orreq r0, r0, #(1 << 6)
209 mcreq p15, 0, r0, c1, c0, 1
212 mov r8, r0
216 mov r0, #SCU_PM_NORMAL
258 mrc p15, 0, r0, c0, c0, 5
259 ands r0, r0, #0x0f
262 mov r0, #OMAP4_PPA_CPU_ACTRL_SMP_INDEX
271 cmp r0, #0x0 @ API returns 0 on success.
275 mrc p15, 0, r0, c1, c0, 1
276 tst r0, #(1 << 6) @ Check SMP bit enabled?
277 orreq r0, r0, #(1 << 6)
278 mcreq p15, 0, r0, c1, c0, 1
291 ldr r0, [r2, #L2X0_CTRL]
292 and r0, #0x0f
293 cmp r0, #1
299 ldr r0, =OMAP4_PPA_L2_POR_INDEX
314 ldr r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
319 ldr r0, [r1, #L2X0_AUXCTRL_OFFSET]
322 mov r0, #0x1