Lines Matching refs:context_offs
67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
365 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
380 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
426 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
475 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
602 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
649 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
672 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
695 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
718 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
741 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
764 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
787 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
810 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
851 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
887 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
932 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
949 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
966 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
983 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1000 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1034 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1047 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1060 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1073 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1086 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1099 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1112 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1125 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1138 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1151 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1164 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1177 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1190 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1230 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1251 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1272 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1293 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1330 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1378 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1400 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1421 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1442 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1469 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1504 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1519 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1543 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1558 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1591 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1623 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1660 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1705 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1726 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1763 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1814 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1829 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1844 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1859 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1874 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1889 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1904 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1919 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1934 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1949 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1964 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1979 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
1994 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2009 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2024 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2062 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2078 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2094 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2110 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2126 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2142 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2158 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2174 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2190 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2206 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2246 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2267 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2284 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2299 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2323 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2337 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2374 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,