96 	u8 i;  in _wakeupgen_clear()  local
98 	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))  in _wakeupgen_clear()
101 	val = wakeupgen_readl(i, cpu);  in _wakeupgen_clear()
103 	wakeupgen_writel(val, i, cpu);  in _wakeupgen_clear()
109 	u8 i;  in _wakeupgen_set()  local
111 	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))  in _wakeupgen_set()
114 	val = wakeupgen_readl(i, cpu);  in _wakeupgen_set()
116 	wakeupgen_writel(val, i, cpu);  in _wakeupgen_set()
150 	u8 i;  in _wakeupgen_save_masks()  local
152 	for (i = 0; i < irq_banks; i++)  in _wakeupgen_save_masks()
153 		per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);  in _wakeupgen_save_masks()
158 	u8 i;  in _wakeupgen_restore_masks()  local
160 	for (i = 0; i < irq_banks; i++)  in _wakeupgen_restore_masks()
161 		wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);  in _wakeupgen_restore_masks()
166 	u8 i;  in _wakeupgen_set_all()  local
168 	for (i = 0; i < irq_banks; i++)  in _wakeupgen_set_all()
169 		wakeupgen_writel(reg, i, cpu);  in _wakeupgen_set_all()
198 	u32 i, val;  in omap4_irq_save_context()  local
203 	for (i = 0; i < irq_banks; i++) {  in omap4_irq_save_context()
205 		val = wakeupgen_readl(i, 0);  in omap4_irq_save_context()
206 		sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);  in omap4_irq_save_context()
207 		val = wakeupgen_readl(i, 1);  in omap4_irq_save_context()
208 		sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);  in omap4_irq_save_context()
217 		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);  in omap4_irq_save_context()
218 		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);  in omap4_irq_save_context()
242 	u32 i, val;  in omap5_irq_save_context()  local
244 	for (i = 0; i < irq_banks; i++) {  in omap5_irq_save_context()
246 		val = wakeupgen_readl(i, 0);  in omap5_irq_save_context()
247 		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);  in omap5_irq_save_context()
248 		val = wakeupgen_readl(i, 1);  in omap5_irq_save_context()
249 		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);  in omap5_irq_save_context()
250 		sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);  in omap5_irq_save_context()
251 		sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);  in omap5_irq_save_context()
431 	int i;  in wakeupgen_domain_alloc()  local
442 	for (i = 0; i < nr_irqs; i++)  in wakeupgen_domain_alloc()
443 		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,  in wakeupgen_domain_alloc()
465 	int i;  in wakeupgen_init()  local
508 	for (i = 0; i < irq_banks; i++) {  in wakeupgen_init()
509 		wakeupgen_writel(0, i, CPU0_ID);  in wakeupgen_init()
511 			wakeupgen_writel(0, i, CPU1_ID);  in wakeupgen_init()
520 	for (i = 0; i < max_irqs; i++)  in wakeupgen_init()
521 		irq_target_cpu[i] = boot_cpu;  in wakeupgen_init()