Lines Matching refs:name

157 	.name		  = "l4_cefuse_clkdm",
158 	.pwrdm		  = { .name = "cefuse_pwrdm" },
166 	.name		  = "l4_cfg_clkdm",
167 	.pwrdm		  = { .name = "core_pwrdm" },
176 	.name		  = "tesla_clkdm",
177 	.pwrdm		  = { .name = "tesla_pwrdm" },
188 	.name		  = "l3_gfx_clkdm",
189 	.pwrdm		  = { .name = "gfx_pwrdm" },
200 	.name		  = "ivahd_clkdm",
201 	.pwrdm		  = { .name = "ivahd_pwrdm" },
212 	.name		  = "l4_secure_clkdm",
213 	.pwrdm		  = { .name = "l4per_pwrdm" },
224 	.name		  = "l4_per_clkdm",
225 	.pwrdm		  = { .name = "l4per_pwrdm" },
234 	.name		  = "abe_clkdm",
235 	.pwrdm		  = { .name = "abe_pwrdm" },
244 	.name		  = "l3_instr_clkdm",
245 	.pwrdm		  = { .name = "core_pwrdm" },
252 	.name		  = "l3_init_clkdm",
253 	.pwrdm		  = { .name = "l3init_pwrdm" },
264 	.name		  = "d2d_clkdm",
265 	.pwrdm		  = { .name = "core_pwrdm" },
275 	.name		  = "mpu0_clkdm",
276 	.pwrdm		  = { .name = "cpu0_pwrdm" },
284 	.name		  = "mpu1_clkdm",
285 	.pwrdm		  = { .name = "cpu1_pwrdm" },
293 	.name		  = "l3_emif_clkdm",
294 	.pwrdm		  = { .name = "core_pwrdm" },
303 	.name		  = "l4_ao_clkdm",
304 	.pwrdm		  = { .name = "always_on_core_pwrdm" },
312 	.name		  = "ducati_clkdm",
313 	.pwrdm		  = { .name = "core_pwrdm" },
324 	.name		  = "mpuss_clkdm",
325 	.pwrdm		  = { .name = "mpu_pwrdm" },
335 	.name		  = "l3_2_clkdm",
336 	.pwrdm		  = { .name = "core_pwrdm" },
345 	.name		  = "l3_1_clkdm",
346 	.pwrdm		  = { .name = "core_pwrdm" },
355 	.name		  = "iss_clkdm",
356 	.pwrdm		  = { .name = "cam_pwrdm" },
366 	.name		  = "l3_dss_clkdm",
367 	.pwrdm		  = { .name = "dss_pwrdm" },
378 	.name		  = "l4_wkup_clkdm",
379 	.pwrdm		  = { .name = "wkup_pwrdm" },
388 	.name		  = "emu_sys_clkdm",
389 	.pwrdm		  = { .name = "emu_pwrdm" },
398 	.name		  = "l3_dma_clkdm",
399 	.pwrdm		  = { .name = "core_pwrdm" },