Lines Matching refs:r5
99 mov r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff
100 orr r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00
101 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
158 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
159 bic r5, r5, #PDE_BIT & 0xff
160 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
163 and r5, r5, #PWD_EN_BIT & 0xff
164 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
167 ldr r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
168 orr r5, r5, #SELF_REFRESH_MODE & 0xff000000
169 orr r5, r5, #SELF_REFRESH_MODE & 0x000000ff
170 str r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
173 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
174 orr r5, r5, #IDLE_EMIFS_REQUEST & 0xff
175 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
183 mov r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
184 orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
185 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
192 mov r5, #IDLE_WAIT_CYCLES & 0xff
193 orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
195 subs r5, r5, #1
254 mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
255 orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
256 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]