Lines Matching refs:r4

72 	mov	r4, #0
93 	mov	r4, #CLKGEN_REG_ASM_BASE & 0xff000000
94 	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
95 	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
101 	strh	r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
106 	strh	r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
130 	strh	r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
131 	strh	r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
152 	mov	r4, #TCMIF_ASM_BASE & 0xff000000
153 	orr	r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
154 	orr	r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
158 	ldr	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
160 	str	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
164 	str	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
167 	ldr	r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
170 	str	r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
173 	ldr	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
175 	str	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
178 	mov	r4, #CLKGEN_REG_ASM_BASE & 0xff000000
179 	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
180 	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
185 	strh	r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
190 	strh	r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
209 	strh	r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
210 	strh	r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
227 	mov	r4, #0
248 	mov	r4, #CLKGEN_REG_ASM_BASE & 0xff000000
249 	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
250 	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
256 	strh	r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
261 	strh	r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
358 	strh	r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
359 	strh	r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]