50 			__raw_writel(data, MPMU_WUCRM_PJ);  in mmp2_set_wake()
55 			__raw_writel(data, MPMU_WUCRM_PJ);  in mmp2_set_wake()
66 	__raw_writel(0x0, CIU_REG(0x64));  in pm_scu_clk_disable()
67 	__raw_writel(0x0, CIU_REG(0x68));  in pm_scu_clk_disable()
72 	__raw_writel(val, CIU_REG(0x1c));  in pm_scu_clk_disable()
82 	__raw_writel(0x03003003, CIU_REG(0x64));  in pm_scu_clk_enable()
83 	__raw_writel(0x00303030, CIU_REG(0x68));  in pm_scu_clk_enable()
88 	__raw_writel(val, CIU_REG(0x1c));  in pm_scu_clk_enable()
99 	__raw_writel(0x0000a010, MPMU_CGR_PJ);  in pm_mpmu_clk_disable()
106 	__raw_writel(0xdffefffe, MPMU_CGR_PJ);  in pm_mpmu_clk_enable()
109 	__raw_writel(val, MPMU_PLL2_CTRL1);  in pm_mpmu_clk_enable()
156 	__raw_writel(idle_cfg, APMU_PJ_IDLE_CFG);  in mmp2_pm_enter_lowpower_mode()
157 	__raw_writel(apcr, MPMU_PCR_PJ);	/* 0xfe086000 */  in mmp2_pm_enter_lowpower_mode()
172 	__raw_writel(temp, APMU_SRAM_PWR_DWN);  in mmp2_pm_enter()
232 	__raw_writel(0x5, MPMU_SCCR);  in mmp2_pm_init()
239 	__raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8));  in mmp2_pm_init()
245 	__raw_writel(apcr, MPMU_PCR_PJ);  in mmp2_pm_init()