210 	struct clk_pll_setup pllcfg;  in clk_get_pllrate_from_reg()  local
212 	pllcfg.cco_bypass_b15 = 0;  in clk_get_pllrate_from_reg()
213 	pllcfg.direct_output_b14 = 0;  in clk_get_pllrate_from_reg()
214 	pllcfg.fdbk_div_ctrl_b13 = 0;  in clk_get_pllrate_from_reg()
216 		pllcfg.cco_bypass_b15 = 1;  in clk_get_pllrate_from_reg()
218 		pllcfg.direct_output_b14 = 1;  in clk_get_pllrate_from_reg()
220 		pllcfg.fdbk_div_ctrl_b13 = 1;  in clk_get_pllrate_from_reg()
221 	pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);  in clk_get_pllrate_from_reg()
222 	pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);  in clk_get_pllrate_from_reg()
223 	pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];  in clk_get_pllrate_from_reg()
225 	return clk_check_pll_setup(inputclk, &pllcfg);  in clk_get_pllrate_from_reg()