Lines Matching refs:r11
81 ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
82 teq r11, #0
85 str r6, [r11, #L2X0_CACHE_SYNC]
87 ldr r6, [r11, #L2X0_CACHE_SYNC]
99 ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
100 ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
108 str r9, [r11, r8]
113 ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
114 ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
121 ldr r6, [r11, r7]
123 str r6, [r11, r7]
125 ldr r6, [r11, r7]
130 ldr r6, [r11, r7]
132 str r6, [r11, r7]
134 ldr r6, [r11, r7]
139 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
141 str r7, [r11, #MX6Q_MMDC_MAPSR]
143 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
148 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
150 str r7, [r11, #MX6Q_MMDC_MAPSR]
175 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
176 ldr r6, [r11, #0x0]
177 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
178 ldr r6, [r11, #0x0]
179 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
180 ldr r6, [r11, #0x0]
183 ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
185 str r9, [r11, #MX6Q_SRC_GPR1]
186 str r1, [r11, #MX6Q_SRC_GPR2]
191 ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
196 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
198 str r7, [r11, #MX6Q_MMDC_MAPSR]
201 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
203 str r7, [r11, #MX6Q_MMDC_MAPSR]
206 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
210 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
220 str r6, [r11, r9]
228 str r6, [r11, r9]
230 str r6, [r11, r9]
233 str r6, [r11, r9]
243 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
244 ldr r6, [r11, #MX6Q_GPC_IMR1]
245 ldr r7, [r11, #MX6Q_GPC_IMR2]
246 ldr r8, [r11, #MX6Q_GPC_IMR3]
247 ldr r9, [r11, #MX6Q_GPC_IMR4]
250 str r10, [r11, #MX6Q_GPC_IMR1]
251 str r10, [r11, #MX6Q_GPC_IMR2]
252 str r10, [r11, #MX6Q_GPC_IMR3]
253 str r10, [r11, #MX6Q_GPC_IMR4]
261 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
262 ldr r10, [r11, #MX6Q_CCM_CCR]
265 str r10, [r11, #MX6Q_CCM_CCR]
268 ldr r10, [r11, #MX6Q_CCM_CCR]
270 str r10, [r11, #MX6Q_CCM_CCR]
273 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
274 str r6, [r11, #MX6Q_GPC_IMR1]
275 str r7, [r11, #MX6Q_GPC_IMR2]
276 str r8, [r11, #MX6Q_GPC_IMR3]
277 str r9, [r11, #MX6Q_GPC_IMR4]
325 ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
327 str r7, [r11, #MX6Q_SRC_GPR1]
328 str r7, [r11, #MX6Q_SRC_GPR2]