Lines Matching refs:r0
81 ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
99 ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
100 ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
102 ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
104 add r7, r7, r0
113 ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
114 ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
155 ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
156 ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
157 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
158 ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
175 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
177 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
179 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
183 ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
191 ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
210 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
212 ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
214 add r8, r8, r0
243 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
261 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
273 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
323 ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
325 ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
330 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]