Lines Matching refs:end
164 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
170 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
176 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
195 .end = DA850_TPCC1_BASE + SZ_32K - 1,
201 .end = DA850_TPTC2_BASE + SZ_1K - 1,
267 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
272 .end = IRQ_DA8XX_I2CINT0,
287 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
292 .end = IRQ_DA8XX_I2CINT1,
323 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
356 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
361 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
366 .end = IRQ_DA8XX_C0_RX_PULSE,
371 .end = IRQ_DA8XX_C0_TX_PULSE,
376 .end = IRQ_DA8XX_C0_MISC_PULSE,
402 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
429 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
436 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
443 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
464 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
471 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
478 .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
499 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
506 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
513 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
562 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
567 .end = IRQ_DA8XX_EVTOUT0,
572 .end = IRQ_DA8XX_EVTOUT1,
577 .end = IRQ_DA8XX_EVTOUT2,
582 .end = IRQ_DA8XX_EVTOUT3,
587 .end = IRQ_DA8XX_EVTOUT4,
592 .end = IRQ_DA8XX_EVTOUT5,
597 .end = IRQ_DA8XX_EVTOUT6,
602 .end = IRQ_DA8XX_EVTOUT7,
648 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
653 .end = IRQ_DA8XX_LCDINT,
674 .end = DA8XX_GPIO_BASE + SZ_4K - 1,
679 .end = IRQ_DA8XX_GPIO8,
700 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
705 .end = IRQ_DA8XX_MMCSDINT0,
710 .end = DA8XX_DMA_MMCSD0_RX,
715 .end = DA8XX_DMA_MMCSD0_TX,
737 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
742 .end = IRQ_DA850_MMCSDINT0_1,
747 .end = DA850_DMA_MMCSD1_RX,
752 .end = DA850_DMA_MMCSD1_TX,
774 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
779 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
784 .end = IRQ_DA8XX_CHIPINT0,
860 .end = DA8XX_RTC_BASE + SZ_4K - 1,
865 .end = IRQ_DA8XX_RTC,
870 .end = IRQ_DA8XX_RTC,
903 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
933 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
938 .end = IRQ_DA8XX_SPINT0,
943 .end = DA8XX_DMA_SPI0_RX,
948 .end = DA8XX_DMA_SPI0_TX,
956 .end = DA830_SPI1_BASE + SZ_4K - 1,
961 .end = IRQ_DA8XX_SPINT1,
966 .end = DA8XX_DMA_SPI1_RX,
971 .end = DA8XX_DMA_SPI1_TX,
1021 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; in da8xx_register_spi_bus()
1031 .end = DA850_SATA_BASE + 0x1fff,
1036 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,