Lines Matching refs:vcpu
15 vcpu .req r0 @ vcpu pointer always in r0 label
147 add r1, vcpu, \offset
167 add r1, vcpu, #VCPU_FIQ_REGS
179 ldr r2, [vcpu, #VCPU_PC]
180 ldr r3, [vcpu, #VCPU_CPSR]
185 ldr r2, [vcpu, #VCPU_USR_SP]
186 ldr r3, [vcpu, #VCPU_USR_LR]
189 add vcpu, vcpu, #(VCPU_USR_REGS)
190 ldm vcpu, {r0-r12}
202 add r2, vcpu, \offset
219 add r2, vcpu, #VCPU_USR_REG(3)
221 add r2, vcpu, #VCPU_USR_REG(0)
226 str r2, [vcpu, #VCPU_USR_SP]
227 str r3, [vcpu, #VCPU_USR_LR]
232 str r2, [vcpu, #VCPU_PC]
233 str r3, [vcpu, #VCPU_CPSR]
264 str r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
265 str r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
266 str r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
267 str r5, [vcpu, #CP15_OFFSET(c3_DACR)]
268 add r2, vcpu, #CP15_OFFSET(c2_TTBR0)
270 add r2, vcpu, #CP15_OFFSET(c2_TTBR1)
272 str r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
273 str r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
274 str r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
292 str r2, [vcpu, #CP15_OFFSET(c13_CID)]
293 str r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
294 str r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
295 str r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
296 str r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
297 str r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
298 str r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
299 str r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
300 str r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
301 str r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
302 str r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
313 str r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
314 add r12, vcpu, #CP15_OFFSET(c7_PAR)
316 str r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)]
317 str r7, [vcpu, #CP15_OFFSET(c10_AMAIR1)]
332 ldr r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
333 add r12, vcpu, #CP15_OFFSET(c7_PAR)
335 ldr r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)]
336 ldr r7, [vcpu, #CP15_OFFSET(c10_AMAIR1)]
347 ldr r2, [vcpu, #CP15_OFFSET(c13_CID)]
348 ldr r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
349 ldr r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
350 ldr r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
351 ldr r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
352 ldr r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
353 ldr r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
354 ldr r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
355 ldr r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
356 ldr r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
357 ldr r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
375 ldr r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
376 ldr r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
377 ldr r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
378 ldr r5, [vcpu, #CP15_OFFSET(c3_DACR)]
379 add r12, vcpu, #CP15_OFFSET(c2_TTBR0)
381 add r12, vcpu, #CP15_OFFSET(c2_TTBR1)
383 ldr r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
384 ldr r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
385 ldr r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
406 ldr r2, [vcpu, #VCPU_KVM]
412 add r11, vcpu, #VCPU_VGIC_CPU
468 ldr r2, [vcpu, #VCPU_KVM]
474 add r11, vcpu, #VCPU_VGIC_CPU
511 ldr r4, [vcpu, #VCPU_KVM]
517 str r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
523 add r5, vcpu, r4
555 ldr r4, [vcpu, #VCPU_KVM]
565 add r5, vcpu, r4
570 ldr r2, [vcpu, #VCPU_TIMER_CNTV_CTL]