Lines Matching refs:r3

25 	VFPFMRX	r3, FPSCR
45 	VFPFMXR FPSCR, r3
65 	mrs	r3, LR_\mode
67 	push	{r2, r3, r4}
80 	push	{r4-r12}	@ r0-r3 are always clobbered
82 	mov	r3, lr
83 	push	{r2, r3}
92 	mrs	r3, r9_fiq
103 	pop	{r2, r3, r4}
105 	msr	LR_\mode, r3
116 	msr	r9_fiq, r3
129 	pop	{r2, r3}
131 	mov	lr, r3
148 	ldm	r1, {r2, r3, r4}
150 	msr	LR_\mode, r3
170 	msr	r9_fiq, r3
180 	ldr	r3, [vcpu, #VCPU_CPSR]
182 	msr	SPSR_cxsf, r3
186 	ldr	r3, [vcpu, #VCPU_USR_LR]
188 	mov	lr, r3
203 	mrs	r3, SP_\mode
206 	stm	r2, {r3, r4, r5}
220 	stm	r2, {r3-r12}
222 	pop	{r3, r4, r5}		@ r0, r1, r2
223 	stm	r2, {r3, r4, r5}
225 	mov	r3, lr
227 	str	r3, [vcpu, #VCPU_USR_LR]
231 	mrs	r3, spsr
233 	str	r3, [vcpu, #VCPU_CPSR]
252 	mrc	p15, 0, r3, c1, c0, 2	@ CPACR
265 	str	r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
278 	mrc	p15, 0, r3, c13, c0, 2	@ TID_URW
293 	str	r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
348 	ldr	r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
361 	mcr	p15, 0, r3, c13, c0, 2	@ TID_URW
376 	ldr	r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
389 	mcr	p15, 0, r3, c1, c0, 2	@ CPACR
451 	add	r3, r11, #VGIC_V2_CPU_LR
455 	str	r6, [r3], #4
477 	ldr	r3, [r11, #VGIC_V2_CPU_HCR]
480 ARM_BE8(rev	r3, r3	)
484 	str	r3, [r2, #GICH_HCR]
490 	add	r3, r11, #VGIC_V2_CPU_LR
492 1:	ldr	r6, [r3], #4
521 	mrrc	p15, 3, rr_lo_hi(r2, r3), c14	@ CNTV_CVAL
524 	strd	r2, r3, [r5]
561 	ldr	r3, [r4, #(KVM_TIMER_CNTVOFF + 4)]
562 	mcrr	p15, 4, rr_lo_hi(r2, r3), c14	@ CNTVOFF
566 	ldrd	r2, r3, [r5]
567 	mcrr	p15, 3, rr_lo_hi(r2, r3), c14	@ CNTV_CVAL
583 	ldr	r3, =HSTR_T(15)
585 	orr	r2, r2, r3		@ Trap CR{15}
587 	bic	r2, r2, r3		@ Don't trap any CRx accesses
607 	mcr	p15, 4, r3, c1, c1, 2
625 	ldr	r3, =(HDCR_TPM|HDCR_TPMCR)
627 	orr	r2, r2, r3		@ Trap some perfmon accesses
629 	bic	r2, r2, r3		@ Don't trap any perfmon accesses