Lines Matching refs:r5
95 bl __lookup_processor_type @ r5=procinfo r9=cpuid
96 movs r10, r5 @ invalid processor (r5=0)?
153 mov r5, #0 @ high TTBR0
231 ldmia r0, {r3, r5, r6}
233 add r5, r5, r0 @ phys __turn_mmu_on
235 mov r5, r5, lsr #SECTION_SHIFT
238 1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base
239 str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
240 cmp r5, r6
241 addlo r5, r5, #1 @ next section
389 movs r10, r5 @ invalid processor?
398 ldmia r4, {r5, r7, r12} @ address to jump to after
399 sub lr, r4, r5 @ mmu has been enabled
402 ARM_BE8(eor r4, r4, r5) @ Swap r5 and r4 in BE:
403 ARM_BE8(eor r5, r4, r5) @ it can be done in 3 steps
404 ARM_BE8(eor r4, r4, r5) @ without using a temp reg.
465 mcrr p15, 0, r4, r5, c2 @ load TTBR0
467 mov r5, #DACR_INIT
468 mcr p15, 0, r5, c3, c0, 0 @ load domain access register