Lines Matching refs:r4
110 ldmia r3, {r4, r8}
111 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
112 add r8, r8, r4 @ PHYS_OFFSET
154 mov r8, r4, lsr #12 @ TTBR1 is swapper_pg_dir pfn
156 mov r8, r4 @ set TTBR1 to swapper_pg_dir
181 pgtbl r4, r8 @ page table address
186 mov r0, r4
201 mov r0, r4
202 add r3, r4, #0x1000 @ first PMD table address
218 add r4, r4, #0x1000 @ point to the PMD tables
220 add r4, r4, #4 @ we only write the bottom word
239 str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
247 add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
250 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
264 add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
268 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
283 addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
290 sub r4, r4, #4 @ Fixup page table pointer
306 add r0, r4, r3
334 add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
344 add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
347 add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
352 sub r4, r4, #0x1000 @ point to the PGD table
397 adr r4, __secondary_data
398 ldmia r4, {r5, r7, r12} @ address to jump to after
399 sub lr, r4, r5 @ mmu has been enabled
401 ldrd r4, [r3, #0] @ get secondary_data.pgdir
402 ARM_BE8(eor r4, r4, r5) @ Swap r5 and r4 in BE:
403 ARM_BE8(eor r5, r4, r5) @ it can be done in 3 steps
404 ARM_BE8(eor r4, r4, r5) @ without using a temp reg.
465 mcrr p15, 0, r4, r5, c2 @ load TTBR0
469 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
513 mov r4, #0x41000000
514 orr r4, r4, #0x0000b000
515 orr r4, r4, #0x00000020 @ val 0x4100b020
516 teq r3, r4 @ ARM 11MPCore?
526 mov r4, #0x41000000
527 orr r4, r4, #0x0000c000
528 orr r4, r4, #0x00000090
529 teq r3, r4 @ Check for ARM Cortex-A9