Lines Matching refs:r0
142 orr r0, r0, #CR_A
144 bic r0, r0, #CR_A
147 bic r0, r0, #CR_C
150 bic r0, r0, #CR_Z
153 bic r0, r0, #CR_I
156 orr r0, r0, #CR_V
158 bic r0, r0, #CR_V
160 mcr p15, 0, r0, c1, c0, 0 @ write control reg
195 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0
196 and r0, r0, #(MMFR0_PMSA) @ PMSA field
197 teq r0, #(MMFR0_PMSAv7) @ PMSA v7
202 mrc p15, 0, r0, c0, c0, 4 @ MPUIR
203 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU
205 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
208 set_region_nr r0, #MPU_RAM_REGION
211 ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET
214 setup_region r0, r5, r6, MPU_DATA_SIDE @ PHYS_OFFSET, shared, enabled
216 setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
220 set_region_nr r0, #MPU_BG_REGION
223 mov r0, #0 @ BG region starts at 0x0
227 setup_region r0, r5, r6, MPU_DATA_SIDE @ 0x0, BG region, enabled
229 setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
233 set_region_nr r0, #MPU_VECTORS_REGION
236 mov r0, #CONFIG_VECTORS_BASE @ Cover from VECTORS_BASE
241 setup_region r0, r5, r6, MPU_DATA_SIDE @ VECTORS_BASE, PL0 NA, enabled
243 setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled
247 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
248 bic r0, r0, #CR_BR @ Disable the 'default mem-map'
249 orr r0, r0, #CR_M @ Set SCTRL.M (MPU on)
250 mcr p15, 0, r0, c1, c0, 0 @ Enable MPU