466 		struct iop3xx_dma_desc_ctrl field;  in iop_desc_init_memcpy()  member
470 	u_desc_ctrl.field.mem_to_mem_en = 1;  in iop_desc_init_memcpy()
471 	u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */  in iop_desc_init_memcpy()
472 	u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;  in iop_desc_init_memcpy()
484 		struct iop3xx_aau_desc_ctrl field;  in iop_desc_init_memset()  member
488 	u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */  in iop_desc_init_memset()
489 	u_desc_ctrl.field.dest_write_en = 1;  in iop_desc_init_memset()
490 	u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;  in iop_desc_init_memset()
502 		struct iop3xx_aau_desc_ctrl field;  in iop3xx_desc_init_xor()  member
508 		u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */  in iop3xx_desc_init_xor()
519 		if (!u_desc_ctrl.field.blk_ctrl) {  in iop3xx_desc_init_xor()
521 			u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */  in iop3xx_desc_init_xor()
533 		if (!u_desc_ctrl.field.blk_ctrl)  in iop3xx_desc_init_xor()
534 			u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */  in iop3xx_desc_init_xor()
551 		if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)  in iop3xx_desc_init_xor()
552 			u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */  in iop3xx_desc_init_xor()
555 	u_desc_ctrl.field.dest_write_en = 1;  in iop3xx_desc_init_xor()
556 	u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */  in iop3xx_desc_init_xor()
557 	u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;  in iop3xx_desc_init_xor()
579 		struct iop3xx_aau_desc_ctrl field;  in iop_desc_init_zero_sum()  member
589 		u_desc_ctrl.field.dest_write_en = 0;  in iop_desc_init_zero_sum()
590 		u_desc_ctrl.field.zero_result_en = 1;  in iop_desc_init_zero_sum()
591 		u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;  in iop_desc_init_zero_sum()
615 		struct iop3xx_aau_desc_ctrl field;  in iop_desc_init_null_xor()  member
621 		u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */  in iop_desc_init_null_xor()
625 		if (!u_desc_ctrl.field.blk_ctrl) {  in iop_desc_init_null_xor()
627 			u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */  in iop_desc_init_null_xor()
632 		if (!u_desc_ctrl.field.blk_ctrl)  in iop_desc_init_null_xor()
633 			u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */  in iop_desc_init_null_xor()
637 		if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)  in iop_desc_init_null_xor()
638 			u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */  in iop_desc_init_null_xor()
641 	u_desc_ctrl.field.dest_write_en = 0;  in iop_desc_init_null_xor()
642 	u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;  in iop_desc_init_null_xor()