Lines Matching refs:clock
105 clock-names = "wdogclk", "apb_pclk";
113 clock-names = "pxlclk";
120 clock-names = "apb_pclk";
171 clock-names = "apb_pclk";
183 clock-names = "apb_pclk";
219 /* Reference 24MHz clock */
220 compatible = "fixed-clock";
221 #clock-cells = <0>;
222 clock-frequency = <24000000>;
223 clock-output-names = "oscclk6a";
231 /* A15 PLL 0 reference clock */
235 #clock-cells = <0>;
236 clock-output-names = "oscclk0";
240 /* A15 PLL 1 reference clock */
244 #clock-cells = <0>;
245 clock-output-names = "oscclk1";
249 /* A7 PLL 0 reference clock */
253 #clock-cells = <0>;
254 clock-output-names = "oscclk2";
258 /* A7 PLL 1 reference clock */
262 #clock-cells = <0>;
263 clock-output-names = "oscclk3";
267 /* External AXI master clock */
271 #clock-cells = <0>;
272 clock-output-names = "oscclk4";
276 /* HDLCD PLL reference clock */
280 #clock-cells = <0>;
281 clock-output-names = "oscclk5";
285 /* Static memory controller clock */
289 #clock-cells = <0>;
290 clock-output-names = "oscclk6";
294 /* SYS PLL reference clock */
298 #clock-cells = <0>;
299 clock-output-names = "oscclk7";
303 /* DDR2 PLL reference clock */
307 #clock-cells = <0>;
308 clock-output-names = "oscclk8";
388 clock-names = "apb_pclk";
402 clock-names = "apb_pclk";
452 clock-names = "apb_pclk";
517 clock-names = "apb_pclk";
531 clock-names = "apb_pclk";
545 clock-names = "apb_pclk";
559 clock-names = "apb_pclk";
573 clock-names = "apb_pclk";