Lines Matching refs:ALT2
108 keyin0 = <&pio0 2 ALT2 IN>;
109 keyin1 = <&pio0 3 ALT2 IN>;
110 keyin2 = <&pio0 4 ALT2 IN>;
111 keyin3 = <&pio2 6 ALT2 IN>;
113 keyout0 = <&pio1 6 ALT2 OUT>;
114 keyout1 = <&pio1 7 ALT2 OUT>;
115 keyout2 = <&pio0 6 ALT2 OUT>;
116 keyout3 = <&pio2 7 ALT2 OUT>;
133 sda = <&pio3 2 ALT2 BIDIR>;
134 scl = <&pio3 1 ALT2 BIDIR>;
142 ir = <&pio4 0 ALT2 IN>;
356 tx = <&pio17 4 ALT2 OUT>;
357 rx = <&pio17 5 ALT2 IN>;
365 mdint = <&pio13 6 ALT2 IN BYPASS 0>;
366 txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
368 txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
369 txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
370 txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
371 txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
373 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
374 txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
375 crs = <&pio15 2 ALT2 IN BYPASS 1000>;
376 col = <&pio15 3 ALT2 IN BYPASS 1000>;
377 mdio = <&pio15 4 ALT2 OUT BYPASS 3000>;
378 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
380 rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
381 rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
382 rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
383 rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
384 rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
385 rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
386 rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
387 phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>;
394 mdint = <&pio13 6 ALT2 IN BYPASS 0>;
395 mdio = <&pio15 4 ALT2 OUT BYPASS 3000>;
396 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
397 txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
399 txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
400 txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
401 txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
402 txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
403 txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
404 txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
405 txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
406 txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
408 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
409 txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
410 crs = <&pio15 2 ALT2 IN BYPASS 1000>;
411 col = <&pio15 3 ALT2 IN BYPASS 1000>;
412 rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
413 rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
415 rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
416 rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
417 rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
418 rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
419 rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
420 rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
421 rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
422 rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
424 rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;