Lines Matching refs:ALT1
124 sda = <&pio4 6 ALT1 BIDIR>;
125 scl = <&pio4 5 ALT1 BIDIR>;
150 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
151 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
152 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
153 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
154 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
155 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
156 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
157 col = <&pio0 7 ALT1 IN BYPASS 1000>;
158 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
159 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
160 crs = <&pio1 2 ALT1 IN BYPASS 1000>;
161 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
162 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
163 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
164 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
165 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
166 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
167 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
168 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
169 phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>;
175 txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>;
176 txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>;
177 txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>;
178 txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>;
179 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
180 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
181 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
182 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
183 rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
184 rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
185 rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
186 rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
188 rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>;
189 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
277 sda = <&pio9 3 ALT1 BIDIR>;
278 scl = <&pio9 2 ALT1 BIDIR>;
286 sda = <&pio12 1 ALT1 BIDIR>;
287 scl = <&pio12 0 ALT1 BIDIR>;
425 clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>;