Lines Matching refs:clock
13 #include <dt-bindings/clock/sh73a0-clock.h>
29 clock-frequency = <1196000000>;
36 clock-frequency = <1196000000>;
85 clock-names = "fck";
304 clock-names = "sci_ick";
314 clock-names = "sci_ick";
324 clock-names = "sci_ick";
334 clock-names = "sci_ick";
344 clock-names = "sci_ick";
354 clock-names = "sci_ick";
364 clock-names = "sci_ick";
374 clock-names = "sci_ick";
384 clock-names = "sci_ick";
548 compatible = "fixed-clock";
549 #clock-cells = <0>;
550 clock-frequency = <32768>;
551 clock-output-names = "extalr";
554 compatible = "fixed-clock";
555 #clock-cells = <0>;
556 clock-frequency = <26000000>;
557 clock-output-names = "extal1";
560 compatible = "fixed-clock";
561 #clock-cells = <0>;
562 clock-output-names = "extal2";
565 compatible = "fixed-clock";
566 #clock-cells = <0>;
567 clock-output-names = "extcki";
570 compatible = "fixed-clock";
571 #clock-cells = <0>;
572 clock-frequency = <0>;
573 clock-output-names = "fsiack";
576 compatible = "fixed-clock";
577 #clock-cells = <0>;
578 clock-frequency = <0>;
579 clock-output-names = "fsibck";
587 #clock-cells = <1>;
588 clock-output-names = "main", "pll0", "pll1", "pll2",
596 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
602 #clock-cells = <0>;
603 clock-output-names = "vclk1";
606 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
612 #clock-cells = <0>;
613 clock-output-names = "vclk2";
616 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
622 #clock-cells = <0>;
623 clock-output-names = "vclk3";
626 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
630 #clock-cells = <0>;
631 clock-output-names = "zb";
634 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
638 #clock-cells = <0>;
639 clock-output-names = "flctlck";
642 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
646 #clock-cells = <0>;
647 clock-output-names = "sdhi0ck";
650 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
654 #clock-cells = <0>;
655 clock-output-names = "sdhi1ck";
658 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
662 #clock-cells = <0>;
663 clock-output-names = "sdhi2ck";
666 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
670 #clock-cells = <0>;
671 clock-output-names = "fsia";
674 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
678 #clock-cells = <0>;
679 clock-output-names = "fsib";
682 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
686 #clock-cells = <0>;
687 clock-output-names = "sub";
690 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
694 #clock-cells = <0>;
695 clock-output-names = "spua";
698 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
702 #clock-cells = <0>;
703 clock-output-names = "spuv";
706 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
710 #clock-cells = <0>;
711 clock-output-names = "msu";
714 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
718 #clock-cells = <0>;
719 clock-output-names = "hsi";
722 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
726 #clock-cells = <0>;
727 clock-output-names = "mfg1";
730 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
734 #clock-cells = <0>;
735 clock-output-names = "mfg2";
738 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
742 #clock-cells = <0>;
743 clock-output-names = "dsit";
746 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
751 #clock-cells = <0>;
752 clock-output-names = "dsi0pck";
757 compatible = "fixed-factor-clock";
759 #clock-cells = <0>;
760 clock-div = <2>;
761 clock-mult = <1>;
762 clock-output-names = "main_div2";
765 compatible = "fixed-factor-clock";
767 #clock-cells = <0>;
768 clock-div = <2>;
769 clock-mult = <1>;
770 clock-output-names = "pll1_div2";
773 compatible = "fixed-factor-clock";
775 #clock-cells = <0>;
776 clock-div = <7>;
777 clock-mult = <1>;
778 clock-output-names = "pll1_div7";
781 compatible = "fixed-factor-clock";
783 #clock-cells = <0>;
784 clock-div = <13>;
785 clock-mult = <1>;
786 clock-output-names = "pll1_div13";
789 compatible = "fixed-factor-clock";
791 #clock-cells = <0>;
792 clock-div = <4>;
793 clock-mult = <1>;
794 clock-output-names = "twd";
802 #clock-cells = <1>;
803 clock-indices = <
806 clock-output-names =
820 #clock-cells = <1>;
821 clock-indices = <
828 clock-output-names =
839 #clock-cells = <1>;
840 clock-indices = <
847 clock-output-names =
864 #clock-cells = <1>;
865 clock-indices = <
875 clock-output-names =
885 #clock-cells = <1>;
886 clock-indices = <
890 clock-output-names =
897 #clock-cells = <1>;
898 clock-indices = <
901 clock-output-names =