Lines Matching refs:gcc
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
227 clocks = <&gcc GSBI1_H_CLK>;
241 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
253 clocks = <&gcc GSBI2_H_CLK>;
265 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
277 clocks = <&gcc GSBI3_H_CLK>;
288 clocks = <&gcc GSBI3_QUP_CLK>,
289 <&gcc GSBI3_H_CLK>;
299 clocks = <&gcc GSBI6_H_CLK>;
310 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
321 clocks = <&gcc GSBI7_H_CLK>;
333 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
408 gcc: clock-controller@900000 { label
409 compatible = "qcom,gcc-apq8064";
460 clocks = <&gcc USB_HS1_XCVR_CLK>,
461 <&gcc USB_HS1_H_CLK>;
464 resets = <&gcc USB_HS1_RESET>;
475 clocks = <&gcc USB_HS3_XCVR_CLK>,
476 <&gcc USB_HS3_H_CLK>;
479 resets = <&gcc USB_HS3_RESET>;
490 clocks = <&gcc USB_HS4_XCVR_CLK>,
491 <&gcc USB_HS4_H_CLK>;
494 resets = <&gcc USB_HS4_RESET>;
536 clocks = <&gcc SATA_PHY_CFG_CLK>;
547 clocks = <&gcc SFAB_SATA_S_H_CLK>,
548 <&gcc SATA_H_CLK>,
549 <&gcc SATA_A_CLK>,
550 <&gcc SATA_RXOOB_CLK>,
551 <&gcc SATA_PMALIVE_CLK>;
558 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
559 <&gcc SATA_PMALIVE_CLK>;
571 clocks = <&gcc SDC1_H_CLK>;
581 clocks = <&gcc SDC3_H_CLK>;
591 clocks = <&gcc SDC4_H_CLK>;
609 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
627 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
645 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;