Lines Matching refs:clock
43 clocks = <&clock CLK_ARM_CLK>;
44 clock-names = "cpu";
45 clock-latency = <160000>;
105 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
106 clock-names = "fin_pll", "mct";
121 clock: clock-controller@10030000 { label
122 compatible = "samsung,exynos4210-clock";
124 #clock-cells = <1>;
155 clocks = <&clock CLK_TMU_APBIF>;
156 clock-names = "tmu_apbif";
186 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
187 clock-names = "sclk_fimg2d", "fimg2d";
193 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
194 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
195 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
224 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
226 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
227 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
228 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
234 clocks = <&clock CLK_PPMULCD1>;
235 clock-names = "ppmu";
244 clock-names = "sysmmu", "master";
245 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
255 clock-names = "sysmmu", "master";
256 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
275 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
277 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
278 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
279 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
280 #clock-cells = <1>;