Lines Matching refs:c0
33 mcr p14, 0, \ch, c0, c5, 0
39 mcr p14, 0, \ch, c8, c0, 0
45 mcr p14, 0, \ch, c1, c0, 0
93 mrc p15, 0, r0, c1, c0
622 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
623 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
624 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
627 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
628 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
634 mrc p15, 0, r0, c1, c0, 0 @ read control reg
639 mcr p15, 0, r0, c1, c0, 0 @ write control reg
651 mcr p15, 0, r0, c2, c0, 0 @ cache on
652 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
655 mcr p15, 0, r0, c5, c0, 0 @ access permission
658 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
663 mrc p15, 0, r0, c1, c0, 0 @ read control reg
668 mcr p15, 0, r0, c1, c0, 0 @ write control reg
671 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
724 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
727 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
733 mcr p15, 7, r0, c15, c0, 0
744 mrc p15, 0, r0, c1, c0, 0 @ read control reg
757 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
766 mrc p15, 0, r0, c1, c0, 0 @ read control reg
775 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
780 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
781 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
782 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
785 mcr p15, 0, r0, c1, c0, 0 @ load control register
786 mrc p15, 0, r0, c1, c0, 0 @ and read it back
799 mrc p15, 0, r0, c1, c0, 0 @ read control reg
812 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
813 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
816 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
817 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
839 mrc p15, 0, r9, c0, c0 @ get processor ID
1046 mrc p15, 0, r0, c1, c0
1048 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1056 mrc p15, 0, r0, c1, c0
1058 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1060 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1065 mrc p15, 0, r0, c1, c0
1067 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1075 mrc p15, 0, r0, c1, c0
1081 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1146 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1155 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1166 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1168 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1197 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1219 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1253 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3