Lines Matching refs:errata
1033 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1042 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1051 bool "ARM errata: Stale prediction on replaced interworking branch"
1067 bool "ARM errata: Processor deadlock when a false hazard is created"
1081 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1094 bool "ARM errata: DMB operation may be faulty"
1107 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1122 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1133 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1145 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1159 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1170 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1181 bool "ARM errata: no automatic Store Buffer drain"
1192 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1204 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1218 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1228 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1238 bool "ARM errata: incorrect instructions may be executed from loop buffer"