Lines Matching refs:pipes

18   -- Seekable pipes
24   -- Channels, pipes, and the message channel
86 project to another (the number of data pipes needed in each direction and
91 Xillybus presents independent data streams, which resemble pipes or TCP/IP
126 possibly pressing CTRL-C as some stage, even though the xillybus_* pipes have
129 The driver and hardware are designed to behave sensibly as pipes, including:
139 device files are treated like two independent pipes (except for sharing a
145 Xillybus pipes are configured (on the IP core) to be either synchronous or
155 For FPGA to host pipes, asynchronous pipes allow data transfer from the FPGA
157 has been requested by a read() call. On synchronous pipes, only the amount
160 In summary, for synchronous pipes, data between the host and FPGA is
170 Seekable pipes
229   Seekable pipes above.
257 Channels, pipes, and the message channel
260 Each of the (possibly bidirectional) pipes presented to the user is allocated
262 and pipes is necessary only because of channel 0, which is used for interrupt-
303 Note that the issue of partial buffer flushing is irrelevant for pipes having
304 the "synchronous" attribute nonzero, since synchronous pipes don't allow data
314 with no issues. Writing single bytes to pipes with 16 or 32 bit granularity
328 As mentioned earlier, the number of pipes that are created when the driver
358 the IDT. The driver relies on a rule that the pipes are sorted with decreasing