Lines Matching refs:which

23 present some of the problems which arise and solutions available, giving
27 timekeeping which may be difficult to find elsewhere, specifically,
42 channels which can be programmed to deliver periodic or one-shot interrupts.
85  line is set high, a countdown is initiated (which does not stop if the gate is
86  lowered), during which the output is set low.  When the count reaches zero,
96  determines the length of the pulse, which alternates between high and low
104  which generates sine-like tones by low-pass filtering the square wave output.
113  (which does not stop if the gate is lowered).  When the counter reaches zero,
182 The second device which was available in the original PC was the MC146818 real
186 The RTC is accessed through CMOS variables, which uses an index register to
187 control which bytes are read.  Since there is only one index register, read
192 The RTC generates an interrupt which is usually routed to IRQ 8.  The interrupt
293 time source which is independent of local variation (as there is only one HPET
303 timing chips built into the cards which may have registers which are accessible
315 instruction cycles issued by the processor, which can be used as a measure of
319 The TSC is represented internally as a 64-bit MSR which can be read with the
329 means of the CR4.TSD bit, which when enabled, disables CPL > 0 TSC access.
331 Some vendors have implemented an additional instruction, RDTSCP, which returns
332 atomically not just the TSC, but an indicator which corresponds to the
338 Both VMX and SVM provide extension fields in the virtualization hardware which
357 values are read from the same clock, which generally only is possible on single
362 As touched on already, CPUs which arrive later than the boot time of the system
382 clock frequency and harmonics of it, which may be required to pass FCC
392 a state, resulting in a TSC which is behind that of other CPUs when execution
429 instructions, which is enough for full virtualization of TSC in any manner.  In
437 instructions, which is enough for full virtualization of TSC in any manner.  In
484 is selected, such as 1000 HZ, which is unfortunately the default for many Linux
488 to simply ignore it.  Guests which have a separate time source for tracking
510 potentially unsynchronized source.  One issue which is not unique to the TSC,
515 which may execute instructions out of order.  Such execution is called
535 Due to non-serialized reads, you may actually end up with a range which
543 the kernel time, which is expressed in the theoretically high resolution
544 timespec - but which advances in much larger granularity intervals, sometimes
554 First, the migration itself may take time, during which interrupts cannot be
555 delivered, and after which, the guest time may need to be caught up.  NTP may
579 paravirtualized scheduler clock, which reveals the true amount of CPU time for
580 which a virtual machine has been running.
596 adequately virtualized without a full real-time operating system, which would
610 problems would require completely isolated virtual time which may not track