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16 One of the most complicated parts of the X86 platform, and specifically,
17 the virtualization of this platform is the plethora of timing devices available
18 and the complexity of emulating those devices. In addition, virtualization of
19 time introduces a new set of challenges because it introduces a multiplexed
20 division of time beyond the control of the guest CPU.
23 present some of the problems which arise and solutions available, giving
24 specific recommendations for certain classes of KVM guests.
26 The purpose of this document is to collect data and information relevant to
40 One of the first timer devices available is the programmable interrupt timer,
46 speaker. Now the PIT is typically integrated as part of an emulated chipset
96 determines the length of the pulse, which alternates between high and low
118 command port, 0x43 is used to set the counter and mode for each of the three
157 Latch combination of counters into corresponding ports
164 Latch combination of counter mode into corresponding ports
169 The output of ports 0x40-0x42 following this command will be:
188 of the CMOS and read of the RTC require lock protection (in addition, it is
190 access, as they could corrupt kernel reads and writes of CMOS memory).
194 interrupts after an update of the CMOS registers by the MC146818 is complete.
195 The type of interrupt is signalled in the RTC status registers.
201 The clock uses a 32.768kHz crystal, so bits 6-4 of register A should be
214 06h byte Current day of week (BCD)
215 07h byte Current day of month (BCD)
261 as part of the Advanced Programmable Interrupt Controller. The APIC is
266 in practice, many bugs and glitches have occurred due to the special nature of
268 the use of the APIC and that workarounds may be required. In addition, some of
270 extra overhead incurred from extra reads of memory-mapped I/O or additional
274 avoid repetition of the detail here. It should be pointed out that the APIC
276 of one-shot or periodic operation, and is based on the bus clock divided down
282 support of the X86 PC. It remains to be seen whether that will be the case, as
283 the de facto standard of PC hardware is to emulate these older devices. Some
293 time source which is independent of local variation (as there is only one HPET
297 Detailed specification of the HPET is beyond the current scope of this
306 general frowned upon as not playing by the agreed rules of the game. Such a
315 instruction cycles issued by the processor, which can be used as a measure of
316 time. In practice, due to a number of problems, it is the most complicated
322 was only possible to write the low 32-bits of the 64-bit counter, and the upper
323 32-bits of the counter were cleared. Now, however, on Intel processors family
329 means of the CR4.TSD bit, which when enabled, disables CPL > 0 TSC access.
333 processor number. This can be used to index into an array of TSC variables to
335 The presence of this instruction must be determined by consulting CPUID feature
346 platforms, the TSCs of different CPUs may start at different times depending
353 write the full 64-bits of the TSC, it may be impossible to match the TSC in
354 newly arriving CPUs to that of the rest of the system, resulting in
362 As touched on already, CPUs which arrive later than the boot time of the system
363 may not have a TSC value that is synchronized with the rest of the system.
365 to a value matching the rest of the system, but a perfect match is usually not
366 a guarantee. This can have the effect of bringing a system from a state where
380 In addition, very large systems may deliberately slew the clocks of individual
382 clock frequency and harmonics of it, which may be required to pass FCC
390 C-states, or idling states of the processor, especially C1E and deeper sleep
392 a state, resulting in a TSC which is behind that of other CPUs when execution
404 known other than falling within a range of values. In this case, the TSC will
406 external clock to be a usable source of time.
416 than that of non-halted processors. AMD Turion processors are known to have
421 External signals given to the processor may also have the effect of stopping
428 VMX provides conditional trapping of RDTSC, RDMSR, WRMSR and RDTSCP
429 instructions, which is enough for full virtualization of TSC in any manner. In
436 SVM provides conditional trapping of RDTSC, RDMSR, WRMSR and RDTSCP
437 instructions, which is enough for full virtualization of TSC in any manner. In
459 Timekeeping is especially problematic for virtualization because a number of
461 the host and, potentially, a number of virtual machines. Thus the virtual
462 operating system does not run with 100% usage of the CPU, despite the fact that
466 at any time. This causes problems as the passage of real time, the injection
467 of machine interrupts and the associated clock sources are no longer completely
474 solving many of these problems on bare metal.
478 One of the most immediate problems that occurs with legacy operating systems
479 is that the system timekeeping routines are often designed to keep track of
482 be able to deliver the proper number of interrupts per second, and so guest
489 'wall clock' or 'real time' may not need any adjustment of their interrupts to
494 solution to the problem has risen: the guest may need to become aware of lost
496 implementation of this policy in Linux has been extremely error prone, and a
497 number of buggy variants of lost tick compensation are distributed across
500 Windows uses periodic RTC clocking as a means of keeping time internally, and
507 As the highest precision time source available, the cycle counter of the CPU
511 but is highlighted because of its very precise nature is sampling delay. By
513 possible for the counter to be read ahead of the actual use of the result.
514 This is a consequence of the superscalar execution of the instruction stream,
515 which may execute instructions out of order. Such execution is called
523 it may be necessary for an implementation to guard against "backwards" reads of
529 Additionally, this lack of serialization from the TSC poses another challenge
530 when using results of the TSC when measured against another time source. As
531 the TSC is much higher precision, many possible values of the TSC may be read
537 calibrated against an external value may have a range of valid values.
545 at the rate of jiffies, and possibly in catchup modes, at a much larger step.
547 This aliasing requires care in the computation and recalibration of kvmclock
553 Migration of a virtual machine raises problems for timekeeping in two ways.
562 migrating to a faster machine may preclude the use of a passthrough TSC, as a
563 faster clock cannot be made visible to a guest without the potential of time
564 advancing faster than usual. A slower clock is less of a problem, as it can
571 Since scheduling may be based on precise timing and firing of interrupts, the
572 scheduling algorithms of an operating system may be adversely affected by
575 causes of virtualization exits, possible context switch), this may not always
576 be the case. The effect of this has not been well studied.
579 paravirtualized scheduler clock, which reveals the true amount of CPU time for
586 misinterpretation of the passage of real time. Usually, these warnings are
606 guest about the host in anything but a perfect implementation of virtualized
607 time. This may allow the guest to infer the presence of a hypervisor (as in a