Lines Matching refs:may

27 timekeeping which may be difficult to find elsewhere, specifically,
267 the APIC CPU-local memory-mapped hardware.  Beware that CPU errata may affect
268 the use of the APIC and that workarounds may be required.  In addition, some of
271 functionality that may be more computationally expensive to implement.
284 systems designated as legacy free may support only the HPET as a hardware timer
303 timing chips built into the cards which may have registers which are accessible
346 platforms, the TSCs of different CPUs may start at different times depending
350 The BIOS may attempt to resynchronize the TSCs during the poweron process and
351 the operating system or other system software may attempt to do this as well.
353 write the full 64-bits of the TSC, it may be impossible to match the TSC in
355 unsynchronized TSCs.  This may be done by BIOS or system software, but in
363 may not have a TSC value that is synchronized with the rest of the system.
364 Either system software, BIOS, or SMM code may actually try to establish the TSC
368 small, may be exposed to the OS and any virtualization environment.
377 exact clock and bus design, the drift may or may not be fixed in absolute
378 error, and may accumulate over time.
380 In addition, very large systems may deliberately slew the clocks of individual
382 clock frequency and harmonics of it, which may be required to pass FCC
391 states may be problematic for TSC as well.  The TSC may stop advancing in such
396 The TSC in such a case may be corrected by catching it up to a known external
401 To make things slightly more interesting, some CPUs may change frequency.  They
402 may or may not run the TSC at the same rate, and because the frequency change
403 may be staggered or slewed, at some points in time, the TSC rate may not be
414 inactive, the P-state may be raised temporarily to service cache misses from
421 External signals given to the processor may also have the effect of stopping
445 if so, the TSCs in multi-sockets or NUMA systems may still run independently
463 it may very well make that assumption.  It may expect it to remain true to very
465 virtual interrupt sources are disabled, and the machine may still be preempted
470 This same problem can occur on native hardware to a degree, as SMM mode may
472 BIOS, but not in such an extreme fashion.  However, the fact that SMM mode may
480 time by counting periodic interrupts.  These interrupts may come from the PIT
481 or the RTC, but the problem is the same: the host virtualization engine may not
483 time may fall behind.  This is especially problematic if a high interrupt rate
487 There are three approaches to solving this problem; first, it may be possible
489 'wall clock' or 'real time' may not need any adjustment of their interrupts to
490 maintain proper time.  If this is not sufficient, it may be necessary to inject
494 solution to the problem has risen: the guest may need to become aware of lost
515 which may execute instructions out of order.  Such execution is called
520 Since CPUID may actually be virtualized by a trap and emulate mechanism, this
522 accurate time stamp counter reading may therefore not always be available, and
523 it may be necessary for an implementation to guard against "backwards" reads of
531 the TSC is much higher precision, many possible values of the TSC may be read
534 That is, you may read (T,T+10) while external clock C maintains the same value.
535 Due to non-serialized reads, you may actually end up with a range which
537 calibrated against an external value may have a range of valid values.
538 Re-calibrating this computation may actually cause time, as computed after the
554 First, the migration itself may take time, during which interrupts cannot be
555 delivered, and after which, the guest time may need to be caught up.  NTP may
560 clock is exposed) may now be running at different rates, requiring compensation
562 migrating to a faster machine may preclude the use of a passthrough TSC, as a
571 Since scheduling may be based on precise timing and firing of interrupts, the
572 scheduling algorithms of an operating system may be adversely affected by
575 causes of virtualization exits, possible context switch), this may not always
584 Watchdog timers, such as the lock detector in Linux may fire accidentally when
587 spurious and can be ignored, but in some circumstances it may be necessary to
592 Precise timing and delays may not be possible in a virtualized system.  This
599 The second issue may cause performance problems, but this is unlikely to be a
600 significant issue.  In many cases these delays may be eliminated through
607 time.  This may allow the guest to infer the presence of a hypervisor (as in a
608 red-pill type detection), and it may allow information to leak between guests
610 problems would require completely isolated virtual time which may not track
611 real time any longer.  This may be useful in certain security or QA contexts,