Lines Matching refs:of

5 KVM makes use of some custom MSRs to service some requests.
18 	data: 4-byte alignment physical address of a memory area which must be
19 	in guest RAM. This memory is expected to hold a copy of the following
29 	guaranteed to update this data at the moment of MSR write.
37 		sec: number of seconds for wallclock at time of boot.
39 		nsec: number of nanoseconds for wallclock at time of boot.
44 	Note that although MSRs are per-CPU entities, the effect of this
47 	Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
52 	data: 4-byte aligned physical address of a memory area which must be in
54 	a copy of the following structure:
69 	updates of this structure is arbitrary and implementation-dependent.
80 		of the update of this structure. Guests can subtract this value
81 		from current tsc to derive a notion of elapsed time since the
84 		system_time: a host notion of monotonic time, including sleep
111 		of specific flags has to be checked in 0x40000001 cpuid leaf.
125 	Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
136 	Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
146 	Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
167 	data: Bits 63-6 hold 64-byte aligned physical address of a
174 	First 4 byte of 64 byte memory location will be written to by
175 	the hypervisor at the time of asynchronous page fault (APF)
176 	injection to indicate type of asynchronous page fault. Value
177 	of 1 means that the page referred to by the page fault is not
187 	During delivery of type 1 APF cr2 contains a token that will
191 	kind of token 0xffffffff which tells vcpu that it should wake
203 	data: 64-byte alignment physical address of a memory area which must be
205 	hold a copy of the following structure:
216 	updates of this structure is arbitrary and implementation-dependent.
231 		steal: the amount of time in which this vCPU did not run, in
236 	data: Bit 0 is 1 when PV end of interrupt is enabled on the vcpu; 0
237 	when disabled.  Bit 1 is reserved and must be zero.  When PV end of
239 	physical address of a 4 byte memory area which must be in guest RAM and
242 	The first, least significant bit of 4 byte memory location will be
243 	written to by the hypervisor, typically at the time of interrupt
244 	injection.  Value of 1 means that guest can skip writing EOI to the apic
248 	Value of 0 means that the EOI write is required.